PDF X9410 Data sheet ( Hoja de datos )

Número de pieza	X9410
Descripción	Dual Digitally Controlled Potentiometer
Fabricantes	Xicor
Logotipo
Hay una vista previa y un enlace de descarga de X9410 (archivo pdf) en la parte inferior de esta página. Total 21 Páginas
No Preview Available ! APPLICATION NOTES AVAILABLE AN99 • AN115 • AN120 • AN124 • AN133 • AN134 • AN135 Low Noise/Low Power/SPI Bus X9410 Dual Digitally Controlled Potentiometer (XDCP™) FEATURES • Two potentiometers in one package • SPI serial interface • Register oriented format —Direct read/write/transfer wiper positions —Store as many as four positions per potentiometer • Power supplies —VCC = 2.7V to 5.5V —V+ = 2.7V to 5.5V —V– = –2.7V to –5.5V • Low power CMOS —Standby current < 1µA • High reliability —Endurance–100,000 data changes per bit per register —Register data retention–100 years • 8-bytes of nonvolatile EEPROM memory • 10KΩ resistor arrays • Resolution: 64 taps each pot • 24-lead TSSOP, 24-lead SOIC and 24-pin plastic DIP packages DESCRIPTION The X9410 integrates two digitally controlled potentiometers (XDCP) on a monolithic CMOS integrated microcircuit. The digitally controlled potentiometer is implemented using 63 resistive elements in a series array. Between each element are tap points connected to the wiper terminal through switches. The position of the wiper on the array is controlled by the user through the SPI bus interface. Each potentiometer has associated with it a volatile Wiper Counter Register (WCR) and 4 nonvolatile Data Registers (DR0:DR3) that can be directly written to and read by the user. The contents of the WCR controls the position of the wiper on the resistor array through the switches. Power up recalls the contents of DR0 to the WCR. The XDCP can be used as a three-terminal potentiometer or as a two-terminal variable resistor in a wide variety of applications including control, parameter adjustments, and signal processing. BLOCK DIAGRAM VCC VSS V+ V- HOLD CS SCK SO SI A0 A1 WP Interface and Control Circuitry 8 Data Pot 0 R0 R1 R2 R3 Wiper Counter Register (WCR) VH0/RH0 VL0/RL0 VW0/RW0 Pot 1 R0 R1 R2 R3 Wiper Counter Register (WCR) Resistor Array Pot1 VW1/RW1 VH1/RH1 VL1/RL1 REV 1.1 10/6/00 www.xicor.com Characteristics subject to change without notice. 1 of 21 1 page X9410 Figure 3. Instruction Byte Format Register Select I3 I2 I1 I0 R1 R0 0 P0 Instructions Pot Select The four high order bits of the instruction byte specify the operation. The next two bits (R1 and R0) select one of the four registers that is to be acted upon when a register oriented instruction is issued. The last bit (P0) selects which one of the two potentiometers is to be affected by the instruction. Four of the ten instructions are two bytes in length and end with the transmission of the instruction byte. These instructions are: – XFR Data Register to Wiper Counter Register—This transfers the contents of one speciﬁed Data Register to the associated Wiper Counter Register. – XFR Wiper Counter Register to Data Register—This transfers the contents of the speciﬁed Wiper Counter Register to the speciﬁed associated Data Register. – Global XFR Data Register to Counter Register—This transfers the contents of both speciﬁed Data Registers to the associated Wiper Counter Registers. – Global XFR Wiper Counter Register to Data Register— This transfers the contents of both Wiper Counter Registers to the speciﬁed associated Data Registers. The basic sequence of the two byte instructions is illustrated in Figure 4. These two-byte instructions exchange data between the WCR and one of the data registers. A transfer from a Data Register to a WCR is essentially a write to a static RAM, with the static RAM controlling the wiper position. The response of the wiper to this action will be delayed by tWRL. A transfer from the WCR (current wiper position), to a data register is a write to nonvolatile memory and takes a minimum of tWR to complete. The transfer can occur between one of the two potentiometers and one of its associated registers; or it may occur globally, where the transfer occurs between both potentiometers and one associated register. Five instructions require a three-byte sequence to complete. These instructions transfer data between the host and the X9410; either between the host and one of the data registers or directly between the host and the Wiper Counter Register. These instructions are: – Read Wiper Counter Register—read the current wiper position of the selected pot, – Write Wiper Counter Register—change current wiper position of the selected pot, – Read Data Register—read the contents of the selected data register; – Write Data Register—write a new value to the selected data register. – Read Status—This command returns the contents of the WIP bit which indicates if the internal write cycle is in progress. The sequence of these operations is shown in Figure 5 and Figure 6. The ﬁnal command is Increment/Decrement. It is different from the other commands because it’s length is indeterminate. Once the command is issued, the master can clock the selected wiper up and/or down in one resistor segment steps, thereby providing a ﬁne tuning capability to the host. For each SCK clock pulse (tHIGH) while SI is HIGH, the selected wiper will move one resistor segment towards the VH/RH terminal. Similarly, for each SCK clock pulse while SI is LOW, the selected wiper will move one resistor segment towards the VL/RL terminal. A detailed illustration of the sequence and timing for this operation are shown in Figures 7-8. REV 1.1 10/6/00 www.xicor.com Characteristics subject to change without notice. 5 of 21 5 Page X9410 D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.) Symbol Parameter ICC1 VCC supply current (active) ICC2 ISB ILI ILO VIH VIL VOL VCC supply current (nonvolatile write) VCC current (standby) Input leakage current Output leakage current Input HIGH voltage Input LOW voltage Output LOW voltage Min. Limits Typ. Max. 400 Unit µA 1 mA VCC x 0.7 –0.5 1 10 10 VCC + 0.5 VCC x 0.1 0.4 µA µA µA V V V Test Conditions fSCK = 2MHz, SO = Open, Other Inputs = VSS fSCK = 2MHz, SO = Open, Other Inputs = VSS SCK = SI = VSS, Addr. = VSS VIN = VSS to VCC VOUT = VSS to VCC IOL = 3mA ENDURANCE AND DATA RETENTION Parameter Minimum endurance Data retention Min. 100,000 100 Unit Data changes per bit per register Years CAPACITANCE Symbol COUT(5) CIN(5) Test Output capacitance (SO) Input capacitance (A0, A1, SI, and SCK) POWER-UP TIMING Symbol tPUR(6) tPUW(6) tRVCC Parameter Power-up to initiation of read operation Power-up to initiation of write operation VCC Power up ramp Max. 8 6 Unit pF pF Test Conditions VOUT = 0V VIN = 0V Min. 1 5 0.2 Max. 1 5 50 Unit ms ms V/msec POWER-UP AND POWER-DOWN There are no restrictions on the power-up or power- down sequencing of the bias supplies VCC, V+, and V– provided that all three supplies reach their ﬁnal values within 1msec of each other. However, at all times, the voltages on the potentiometer pins must be less than V+ and more than V–. The recall of the wiper position from nonvolatile memory is not in effect until all supplies reach their ﬁnal value. EQUIVALENT A.C. LOAD CIRCUIT SDA Output 5V 1533Ω 100pF 2.7V 100pF REV 1.1 10/6/00 www.xicor.com Characteristics subject to change without notice. 11 of 21 11 Page

Páginas	Total 21 Páginas
PDF Descargar	[ Datasheet X9410.PDF ]

Hoja de datos destacado

Número de pieza	Descripción	Fabricantes
X9410	Dual Digitally Controlled Potentiometer	Xicor
X9410	Dual Digitally Controlled Potentiometer	Intersil Corporation
X9418	Dual Digitally Controlled Potentiometers	Xicor
X9418	Dual Digitally Controlled Potentiometers	Intersil Corporation

Número de pieza	Descripción	Fabricantes
SLA6805M	High Voltage 3 phase Motor Driver IC.	Sanken
SDC1742	12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters.	Analog Devices

DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares,
permitiéndote verlos en linea o descargarlos en PDF.

DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar