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PDF VG37648041AT Data sheet ( Hoja de datos )
| Número de pieza | VG37648041AT | |
| Descripción | 256M:x4/ x8/ x16 CMOS Synchronous Dynamic RAM | |
| Fabricantes | Vanguard International Semiconductor | |
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VIS
Description
Preliminary
VG37648041AT
256M:x4, x8, x16
CMOS Synchronous Dynamic RAM
The 256Mb DDR SDRAM is a high-speed COMS, dynamic random-access memory containing
268,435,456 bits. It is internally configured as a quad-bank DRAM.
The 256Mb DDR SDRAM uses a double-data-rate architecture to achieve high-speed oper-
ation. The double data rate architecture is essentially a 2n prefetch architecture with an inter-
face designed to transfer two data words per clock cycle at the I/O pins. A single read or write
access for the 256Mb DDR SDRAM effectively consists of a single 2n-bit wide, one clock cycle
data transfer at the internal DRAM core and two corresponding n-bit wide, one-half-clock-cycle
data transfers at the I/O pins.
A bidirectional data strobe (DQS) is transmitted externally, along with data, for use in data
capture at the receiver. DQS is an intermittent strobe transmitted by the DDR SDRAM during
READs and by the memory controller during WRITEs. DQS is edge-aligned with data for
READs and center-aligned with data for WRITEs.
The 256Mb DDR SDRAM operates from a differential clock (CLK and CLK#; the crossing of
CLK going HIGH and CLK# going LOW will be referred to as the postive edge of CLK). Com-
mands (address and control signals) are registered at verey positive edge of CLK. Input data is
registered on both edges of DQS, and output data is referenced to both edges of DQS, as well
as to both edges of CLK.
Read and Write assesses to the DDR SDRAM are burst oriented; accesses start at a
selected location and continue for a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an ACTIVE command, which is then followed
by a READ or WRITE command. The address bits registered coincident with the ACTIVE com-
mand are used to select the bank and row to be accessed (BA0,BA1 select the bank; A0-A12
select the row). The address bits registered coincident with sthe READ or WRITE command
are used to select the starting column location for the burst access.
The DDR SDRAM provides for programmable READ or WRITE burst lengths of 2,4 or 8
locations. An AUTO PRECHARGE function may be enabled to provide a selftimed row pre-
charge that is initiated at the end of the burst access.
As with standard SDRAMs, the pipelined, multibank architecture of DDR SDRAMs allows
for concurrent operation, thereby providing high effective bandwidth by hiding row precharge
and activation time.
The 256Mb DDR SDRAM is designed to operate in either low-power memory systems. An
auto refresh mode is provided, along with a power-saving, power-down mode. All inputs are
compatible with the JEDEC Standard for SSTL_2. All outputs are SSTL_2, Class II compatible.
Initial devices will have a VDD supply of 3.3V (nominal). Eventually, all devices will migrate
to a VDD supply of 2.5V(nominal). During this initial period of product availability. this split will
be vendor and device specific.
This data sheet includes all features and functionality required for JEDEC DDR devices;
options not required but listed, are noted as such. Certain vendors may elect to offer a superset
of this specification by offering improved timing and/or including optional features. Users benefit
from knowing that any system design based on the required aspects of this specification are
supported by all DDR SDRAM vendors; conversely, users seeking to use any superset specifi-
cations bear the responsibility to verify support with individual vendors.
Document : 1G5-0157
Rev.1
Page 1
1 page  
VIS
Preliminary
VG37648041AT
256M:x4, x8, x16
CMOS Synchronous Dynamic RAM
FUNCTIONAL BLOCK DIAGRAM- X8 CONFIGURATION
CKE
CLK#
CLK
CS#
WE#
CAS#
RAS#
Generator
LOGIC
BANK2 BANK3
BANK1
A0-A12
BA0-BA1
MODE REGISTERS
13
15 ADDRESS
RESGISTER
REFRESH
COUNTER
13
13
ROW-
ADDRESS
MUX
13
BANK0
ROW-
ADDRESS
LATCH
&
8192
BANK0
MEMORY
ARRAY
(8192x512x16)
DECODER
SENSE AMPLIFIERS
2
BANK0
2 CONTROL
LOGIC
I/O GATING
DM MASK LOGIC
(x16)
COLUMN
DECODER
COLUMN
9
10
ADDRESS
COUNTER/
LATCH
COL0
1
CLK
DATA
DLL
16 READ
LATCH
8
8
MUX
4
DRVRS
16
16
DQS
GENERATOR
1
COL0
MASK
INPUT
REGISTERS
11
WRITE
FIFO
&
DRIVERS
1
2
8
16
1
8
ctk ctk
out in
8
DATA
8
DQS
1
RCVRS
8
CLK
COL0
1
DO0
DQ7,DM
DQS
Note 1: This Functional Block Diagram is intended to facilitate user understanding of the operation of the
device; it does not necessarily represent an actual circuit implementation.
Note 2: DM is a unidirectional signal (input only)m but is internally loaded to match the load of the bidirec-
tional DQ and DQS signals.
Document : 1G5-0157
Rev.1
Page 5
5 Page 
VIS
Preliminary
VG37648041AT
256M:x4, x8, x16
CMOS Synchronous Dynamic RAM
Table 1
BURST DEFINITION
Burst Length
Starting Column
Address:
A0
2
0
1
A1-A0
00
4 01
10
11
A2 A1 A0
0 00
0 01
0 10
8 0 11
1 00
1 01
110
111
Order of Accesses Within a Burst
0-1
1-0
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0
2-3-4-5-6-7-0-1
3-4-5-6-7-0-1-2
4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4
6-7-0-1-2-3-4-5
7-0-1-2-3-4-5-6
0-1
1-0
0-1-2-3
1-0-3-2
2-3-0-1
3-2-1-0
0-1-2-3-4-5-6-7
1-0-3-2-5-4-7-6
2-3-0-1-6-7-4-5
3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3
5-4-7-6-1-0-3-2
6-7-4-5-2-3-0-1
7-6-5-4-3-2-1-0
NOTE:
1. For a burst length of two, A1-Ai selects the two-data-element block; A0 selects the first access within the block.
2. For a burst length of four, A2-Ai selects the four-data-element block; A0-A1 selects the first access within the block.
3. For a burst length of eight, A3-Ai selects the eight-data-element block; A0-A2 selects the first access within the block.
4.Whenever a boundary of the block is reached within a given sequence above, the following access wraps within the
block.
Document : 1G5-0157
Rev.1
Page 11
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