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PDF TQ1090 Data sheet ( Hoja de datos )

Número de pieza TQ1090
Descripción 11-Output Configurable Clock Buffer
Fabricantes TriQuint Semiconductor 
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No Preview Available ! TQ1090 Hoja de datos, Descripción, Manual

TRIQUINT
S E M I C O N D U C T O R, I N C .
Figure 1. Block Diagram
TQ1090
FBIN S1 REFCLK S0 GND GND GND
11 10 9 8 7 6 5
TEST 12
VDD 13
Q0 14
GND 15
Q1 16
Q2 17
VDD 18
Phase
Detector
VCO
MUX
Divide Logic
S1 S0
÷2
Output Buffers Group C
Group A
Group B
4 VDD
3 Q10
2 Q9
1 GND
28 Q8
27 Q7
26 VDD
19 20
GND Q3
21 22 23
Q4 VDD Q5
24 25
Q6 GND
TriQuint’s TQ1090 is a configurable clock buffer which generates 11
outputs, operating over a wide range of frequencies from 33 MHz to
45MHz, 65 MHz to 90 MHz and 130 MHz to 180 MHz. The outputs are
available at 1x, 2x and 4x, or at 1/2x, 1x and 2x, or at 1/4 x, 1/2 x and
1x the reference clock frequency, fREF.
When one of the Group A outputs (Q0–Q4) is used as feedback to the PLL,
all Group A outputs will be at fREF, all Group B outputs (Q5–Q8) will be at
2x fREF and all Group C outputs (Q9,Q10) will be at 4x fREF. When one of the
Group B outputs is used as feedback to the PLL, all Group A outputs will
be at 1/2 x fREF, all Group B outputs will be at fREF and all Group C outputs
will be at 2x fREF. When one of the Group C outputs is used as feedback to
the PLL, all Group A outputs will be at 1/4 x fREF, all Group B outputs will be
at 1/2 x fREF and all Group C outputs will be at fREF.
A very stable internal Phase-Locked Loop (PLL) provides low-jitter operation.
This completely self-contained PLL requires no external capacitors or
resistors. The PLL’s Voltage-Controlled Oscillator (VCO) has a frequency
range from 260 MHz to 360 MHz. By feeding back one of the output clocks
to FBIN, the PLL continuously maintains frequency and phase synchron-
ization between the reference clock (REFCLK) and each of the outputs.
11-Output
Configurable
Clock Buffer
Features
• Wide frequency range:
33 MHz to 45 MHz
65 MHz to 90 MHz and
130 MHz to 180 MHz
• Output configurations:
four outputs at fREF
four outputs at 2x fREF
two output at 4x fREF or
five outputs at 1/2 x fREF
three outputs at fREF
two outputs at 2x fREF
• Selectable Phase Shift:
–2t, –t, 0, +t (t = 1/fvco)
• Low output-to-output skew:
150 ps (max) within a group
• Near-zero propagation delay
–350 ps ± 500 ps (max) or
–350 ps ±700 ps (max)
• TTL-compatible I/O with 30 mA
output drive
• Ideal for Power PCdesigns
• 28-pin J-lead surface-mount
package
For additional information and latest specifications, see our website: www.triquint.com
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TQ1090 pdf
TQ1090
AC Characteristics
(VDD = +5 V + 5%, TA = 0 °C to +70 °C)
Symbol Input Clock (REFCLK)
t CPWH
t CPWL
t IR
CLK pulse width HIGH
CLK pulse width LOW
Input rise time (0.8 V - 2.0V)
Test Conditions (Figure 3) 1
Figure 4
Figure 4
Min Typ Max Unit
2 --- — ns
2 --- — ns
— — 2.0 ns
Symbol Output Clocks (Q0–Q10)
Test Conditions (Figure 3) 1
Min Typ Max Unit
t OR,t OF
t PD1 2
t PD2 2
t SKEW1 3
t SKEW2 3
t SKEW3 3
t SKEW4 3
t CYC 4
t JP 5
t JR 5
t SYNC 6
Rise/fall time (0.8 V – 2.0V)
Figure 4
350
CLK to FBIN (TQ1090-MC500)
Figure 4
–850
CLK to FBIN (TQ1090-MC700)
Figure 4
–1050
Rise–rise, fall–fall (within group)
Figure 5
Rise–rise, fall–fall (group-to-group, aligned)
Figure 6 (skew2 takes into account skew1) —
Rise–rise, fall–fall (group-to-group, non-aligned) (skew3 takes into account skews1, 2)
Rise–fall, fall–rise
(skew4 takes into account skew3)
Duty-cycle Variation
Figure 4
–1000
Period-to-Period Jitter
Figure 4
Random Jitter
Figure 4
Synchronization Time
–350
–350
60
75
0
80
190
10
1400
+150
+350
150
350
650
1200
+1000
200
400
500
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
µs
Notes: 1. All measurements are tested with a REFCLK having a rise time of 0.5 ns (0.8 V to 2.0 V).
2. The PLL maintains alignment of CLK and FBIN at all times. This specification applies to the rising edge only because the input duty
cycle can vary while the output duty cycle is typically 50/50. The delay tPD is measured at the 1.5 V level between CLK and FBIN.
3. Skew specifies the width of the window in which outputs switch, and is measured at 1.5 V.
Skew 1 is a subset of skew 2. Skew 2 is a subset of skew 3. Skew 3 is a subset of skew 4.
Definition of skew terms:
Rise–rise:
Skew between rising edges (low to high transitions).
Fall–fall:
Skew between falling edges (high to low transitions).
Rise–fall, fall–rise: Skew between rising-to-falling and falling-to-rising edges.
Within a group:
Skew between outputs of the same group (for example, skew among Group A outputs)
Group-to-group:
Skew between outputs of any group (for example, skew between Group A to Group B outputs)
Aligned:
Skew between outputs that are in phase.
Non-aligned:
Skew between outputs that are not in phase.
4. This specification represents the deviation from 50/50 on the outputs.
5. Jitter specifications refer to peak-to-peak value. tJR is the jitter on the output with respect to the reference clock. tJP is the jitter on the
output with respect to the same output’s previous rising edge.
6. tSYNC is the time required for the PLL to synchronize; this assumes the presence of a CLK signal and a connection from one of the
outputs to FBIN.
Figure 3. AC Test Circuit
+5 V
R1 Z
R2
+5 V
R1 Z
R2
Notes:
R1 = 160
R2 = 71
Y+Z=X
Y
FBIN Q0
Q1
Q2
CLK Q10
50
X
+5 V
R1 +5 V
R2 R1
R2
+5 V
R1
R2
For additional information and latest specifications, see our website: www.triquint.com
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