PDF TS68C429A Data sheet ( Hoja de datos )

Número de pieza	TS68C429A
Descripción	CMOS ARINC 429 Multichannel Receiver/ Transmitter MRT
Fabricantes	ATMEL Corporation
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No Preview Available ! Features • 8 Independent Receivers (Rx) • 3 Independent Transmitters (Tx) • Full TS68K Family Microprocessor Interface Compatibility • 16-bit Data-bus • ARINC 429 Interface: “1” and “0” Lines, RZ Code • Support all ARINC 429 Data Rate Transfer and up to 2.5 Mbit/s • Multi Label Capability • Parity Control: Odd, Even, No Parity, Interrupt Capability • Independent Programmable Frequency for Rx and Tx Channels • 8 Messages FIFO per Tx Channel • Independent Interrupt Request Line for Rx and Tx Functions • Vectored Interrupts • Daisy Chain Capability • Direct Addressing of all Registers • Test Modes Capability • 20 MHz Operating Frequency • Self-test Capability for Receiver Label Memories and Transmit FiFO • Low Power: 400 mW Description The TS68C429A is an ARINC 429 controller. It is an enhanced version of the EF 4442 and it is designed to be connected to the new 16- or 32-bit microprocessors, espe- cially these of the Atmel TS68K family. Screening • MIL-STD-883, class B • DESC Drawing 5962-955180 • Atmel Standards CMOS ARINC 429 Multichannel Receiver/ Transmitter (MRT) TS68C429A Application Note • A detailed application note is available “AN 68C429A” on request. R suffix PGA 84 Ceramic Pin Grid Array F suffix CQFP 132 Ceramic Quad Flat Pack Rev. 2120A–HIREL–08/02 1 1 page TS68C429A Figure 1. Signal Description (Continued) Pin Name Type Function RX2L I Receiving “0” line of the channel 2. RX3H I Receiving “1” line of the channel 3. RX3L I Receiving “0” line of the channel 3. RX4H I Receiving “1” line of the channel 4. RX4L I Receiving “0” line of the channel 4. RX5H I Receiving “1” line of the channel 5. RX5L I Receiving “0” line of the channel 5. RX6H I Receiving “1” line of the channel 6. RX6L I Receiving “0” line of the channel 6. RX7H I Receiving “1” line of the channel 7. RX7L I Receiving “0” line of the channel 7. RX8H I Receiving “1” line of the channel 8. RX8L I Receiving “0” line of the channel 8. RESET I This input (active low) will initialize the TS68C429A registers. VCC/GND I These inputs supply power to the chip. The VCC is powered at +5 volts and GND is the ground connection. CLK-SYS I The clock input is a single-phase signal used for internal timing of processor interface. CLK-ARINC I This input provides the timing clock to synchronize received/transmitted messaged. 2120A–HIREL–08/02 5 5 Page TS68C429A Clock Timing Table 6. Clock System (CLK SYS) Symbol Parameter tcyc S tCLS, tCHS tcrS, tcfS Clock Period Clock Pulse Width Rise and Fall Times Min Max Unit 50 2000 ns 20 ns 5 ns Table 7. Clock ARINC (CLK ARINC) Note: Symbol tcyc A tCLA, tCHA tcrA, tcfA 1. tcyc A ≥ 4 x tcyc S. Parameter Cycle Time(1) Clock Pulse Width Rise and Fall Times Min Max Unit 200 8000 ns 240 ns 5 ns AC Electrical Characteristics With VCC = 5 VDC ± 10% VSS = 0 VDC. IEIxx, IEOxx, IACKxx, must be understood as generic signals (xx = RX and TX). Figure 4. Read Cycle Notes: 1. LDS/UDS can be asserted on the next or previous CLK-SYS period after CS goes low but (4) must be met for the next period. 2. The cycle ends when the first of CS, LDS/UDS goes high. 2120A–HIREL–08/02 11 11 Page

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Hoja de datos destacado

Número de pieza	Descripción	Fabricantes
TS68C429A	CMOS ARINC 429 Multichannel Receiver/ Transmitter MRT	ATMEL Corporation
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TS68C429AMF	CMOS ARINC 429 Multichannel Receiver/ Transmitter MRT	ATMEL Corporation
TS68C429AMR	CMOS ARINC 429 Multichannel Receiver/ Transmitter MRT	ATMEL Corporation

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