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PDF RIVA128ZX Data sheet ( Hoja de datos )
| Número de pieza | RIVA128ZX | |
| Descripción | 128-BIT 3D MULTIMEDIA ACCELERATOR | |
| Fabricantes | STMicroelectronics | |
| Logotipo |  |
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® RIVA 128ZX™
128-BIT 3D MULTIMEDIA ACCELERATOR
PRELIMINARY DATA
KEY FEATURES
• Fast 32-bit VGA/SVGA
• High performance 128-bit 2D/GUI/DirectDraw
Acceleration
• Interactive, Photorealistic Direct3D Accelera-
tion with advanced effects
• Pinout backwards compatible with RIVA 128
• Massive 1.6Gbytes/s, 100MHz 128-bit wide
8MByte SGRAM framebuffer interface
• Adds 16Mbit SDRAM support for cost sensitive
8MByte framebuffer applications
• Video Acceleration for DirectDraw/DirectVideo,
MPEG-1/2 and Indeo®
- Planar 4:2:0 and packed 4:2:2 Color Space
Conversion
- X and Y smooth up and down scaling
• 250MHz Palette-DAC supporting up to
1600x1200@85Hz
• NTSC and PAL output with flicker-filter
• Multi-function Video Port and serial interface
• Bus mastering DMA Accelerated Graphics Port
(AGP) 1.0 Interface supporting 133MHz 2X
data transfer mode
• Bus mastering DMA PCI 2.1 interface
• ACPI power management interface support
• 0.35 micron 5LM CMOS
• 300 PBGA
DESCRIPTION
The RIVA128ZX™ offers unparalleled 2D and 3D
performance, meeting all the requirements of the
mainstream PC graphics market and Microsoft’s
PC’97. RIVA128ZX combines all the features of
RIVA 128 plus 8MByte SDRAM and SGRAM
based framestore support and AGP 2X data trans-
fer. It provides the most advanced Direct3D™ ac-
celeration solution and delivers leadership VGA,
2D and Video performance, enabling a range of
applications from 3D games through to DVD, In-
tercast™ and video conferencing.
BLOCK DIAGRAM
1.6 GByte/s
Internal Bus
Bandwidth
DMA Bus
Host
PCI/AGP Interface
FIFO/
DMA
Pusher
VGA
Video Port
DMA Engine
Graphics Engine
128 bit 2D
Direct3D
DMA Engine
Palette DAC
YUV - RGB,
X & Y scaler
8MByte
SDRAM/SGRAM
Interface
CCIR656
Video
Monitor/
TV
128 bit
interface
June 1998
The information in this datasheet is subject to change
7071857 00
1/85
1 page  
128-BIT 3D MULTIMEDIA ACCELERATOR
RIVA128ZX
2 PIN DESCRIPTIONS
2.1 ACCELERATED GRAPHICS PORT (AGP) INTERFACE
Signal
AGPST[2:0]
AGPRBF#
AGPPIPE#
AGPADSTB0,
AGPADSTB1
I/O Description
I AGP status bus providing information from the arbiter to the RIVA128ZX on what it may
do. AGPST[2:0] only have meaning to the RIVA128ZX when PCIGNT# is asserted. When
PCIGNT# is de-asserted these signals have no meaning and must be ignored.
000 Indicates that previously requested low priority read or flush data is being
returned to the RIVA128ZX.
001 Indicates that previously requested high priority read data is being returned to
the RIVA128ZX.
010 Indicates that the RIVA128ZX is to provide low priority write data for a previous
enqueued write command.
011 Indicates that the RIVA128ZX is to provide high priority write data for a previous
enqueued write command.
100 Reserved
101 Reserved
110 Reserved
111 Indicates that the RIVA128ZX has been given permission to start a bus transac-
tion. The RIVA128ZX may enqueue AGP requests by asserting AGPPIPE# or
start a PCI transaction by asserting PCIFRAME#. AGPST[2:0] are always an
output from the Core Logic (AGP chipset) and an input to the RIVA128ZX.
O Read Buffer Full indicates when the RIVA128ZX is ready to accept previously requested
low priority read data or not. When AGPRBF# is asserted the arbiter is not allowed to
return (low priority) read data to the RIVA128ZX. This signal should be pulled up via a
4.7KΩ resistor (although it is supposed to be pulled up by the motherboard chipset).
O Pipelined Read is asserted by RIVA128ZX (when the current master) to indicate a full
width read address is to be enqueued by the target. The RIVA128ZX enqueues one
request each rising clock edge while AGPPIPE# is asserted. When AGPPIPE# is de-
asserted no new requests are enqueued across PCIAD[31:0]. AGPPIPE# is a sustained
tri-state signal from the RIVA128ZX and is an input to the target (the core logic).
I/O Bus strobe signals providing timing for AGP 2X data transfer mode on PCIAD[15:00] and
PCIAD[31:16] respectively. The agent that is supplying data drives these signals.
2.2 PCI 2.1 LOCAL BUS INTERFACE
Signal
PCICLK
PCIRST#
PCIAD[31:0]
I/O Description
I PCI clock. This signal provides timing for all transactions on the PCI bus, except for
PCIRST# and PCIINTA#. All PCI signals are sampled on the rising edge of PCICLK and
all timing parameters are defined with respect to this edge .
I PCI reset. This signal is used to bring registers, sequencers and signals to a consistent
state. When PCIRST# is asserted all output signals are tristated.
I/O 32-bit multiplexed address and data bus. A bus transaction consists of an address phase
followed by one or more data phases.
5/85
5 Page 
128-BIT 3D MULTIMEDIA ACCELERATOR
RIVA128ZX
• Fully supports the “Execute” model on both PCI
and AGP
3.3 2D ACCELERATION
The RIVA128ZX’s 2D rendering engine delivers
industry-leading Windows acceleration perfor-
mance:
• 100MHz 128-bit graphics engine optimized for
single cycle operation into the 128-bit memory
interface supporting up to 1.6GBytes/s
• Acceleration functions optimized for minimal
software overhead on key GDI calls
• Extensive support for DirectDraw in
Windows95 including optimized Direct Frame-
buffer (DFB) access with Write-combining
• Accelerated primitives including BLT, transpar-
ent BLT, stretchBLT, points, lins, lines,
polylines, polygons, fills, patterns, arbitrary
rectangular clipping and improved text render-
ing
• Pipeline optimized for multiple color depths in-
cluding 8, 15, 24, and 30 bits per pixel
• DMA Pusher allows the 2D graphics pipeline to
load rendering methods optimizing
RIVA128ZX/host multi-tasking
• Execution of all 256 Raster Operations (as de-
fined by Microsoft Windows) at 8, 15, 24 and
30-bit color depths
• 15-bit hardware color cursor
• Hardware color dithering
• Multi buffering (Double, Triple, Quad buffering)
for smooth animation
3.4 3D ENGINE
Triangle setup engine
• Setup hardware optimized for Microsoft’s
Direct3D API
• 5Gflop floating point geometry processor
• Slope and setup calculations
• Accepts IEEE Single Precision format used in
Direct3D
• Efficient vertex caching
Rendering engine
The RIVA128ZX Multimedia Accelerator inte-
grates an orthodox 3D rendering pipeline and tri-
angle setup function which not only fully utilizes
the capabilities of the Accelerated Graphics Port,
but also supports advanced texture mapped 3D
over the PCI bus. The RIVA128ZX 3D pipeline of-
fers to Direct3D or similar APIs advanced triangle
rendering capabilities:
• Rendering pipeline optimized for Microsoft’s
Direct3D API
• Perspective correct true-color Gouraud lighting
and texture mapping
• Full 32-bit RGBA texture filter and Gouraud
lighting pixel data path
• Alpha blending for translucency and transpar-
ency
• Sub-pixel accurate texture mapping
• Internal pixel path: up to 24bits, alpha: up to 8
bits
• Texture magnification filtering with high quality
bilinear filtering without performance degrada-
tion
• Texture minification filtering with MIP mapping
without performance degradation
• LOD MIP-mapping: filter shape is dynamically
adjusted based on surface orientation
• Texture sizes from 4 to 2048 texels in either U
or V
• Textures can be looped and paged in real time
for texture animation
• Perspective correct per-pixel fog for atmo-
spheric effects
• Perspective correct specular highlights
• Multi buffering (Double, Triple, Quad buffering)
for smooth 3D animation
• Multipass rendering for environmental mapping
and advanced texturing
3.5 VIDEO PROCESSOR
The RIVA128ZX Palette-DAC pipeline accelerates
full-motion video playback, sustaining 30 frames
per second while retaining the highest quality color
resolution, implementing true bilinear filtering for
scaled video, and compensating for filtering losses
using edge enhancement algorithms.
• Advanced support for DirectDraw (DirectVideo)
in Windows 95
• Back-end hardware video scaling for video con-
ferencing and playback
• Hardware color space conversion (YUV 4:2:2
and 4:2:0)
• Multi-tap X and Y filtering for superior image
quality
• Optional edge enhancement to retain video
sharpness
11/85
11 Page | ||
| Páginas | Total 70 Páginas | |
| PDF Descargar | [ Datasheet RIVA128ZX.PDF ] | |
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