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PDF W144 Data sheet ( Hoja de datos )
| Número de pieza | W144 | |
| Descripción | 440BX AGPset Spread Spectrum Frequency Synthesizer | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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PRELIMINARY
W144
440BX AGPset Spread Spectrum
Frequency Synthesizer
Features
• Maximized EMI suppression using Cypress’s Spread
Spectrum technology
• Single chip system frequency synthesizer for Intel®
440BX AGPset
• Two copies of CPU output
• Six copies of PCI output
• One 48-MHz output for USB
• One 24-MHz output for SIO
• Two buffered reference outputs
• One IOAPIC output
• Thirteen SDRAM outputs provide support for 3 DIMMs
• Supports frequencies up to 150 MHz
• I2C™ interface for programming
• Power management control inputs
Key Specifications
CPU Cycle-to-Cycle Jitter: ......................................... 250 ps
CPU to CPU Output Skew: ........................................ 175 ps
PCI to PCI Output Skew: ............................................ 500 ps
VDDQ3: .................................................................... 3.3V±5%
VDDQ2: .................................................................... 2.5V±5%
SDRAMIN to SDRAM0:11 Delay: ..........................3.7 ns typ.
SDRAM0:11 (leads) to SDRAM_F Skew: ..............0.4 ns typ.
Table 1. Mode Input Table
Mode
0
1
Pin2
PCI_STOP#
REF0
Table 2. Pin Selectable Frequency
Input Address
FS3 FS2 FS1 FS0
1 1 11
1 1 10
1 1 01
1 1 00
1 0 11
1 0 10
1 0 01
1 0 00
0 1 11
0 1 10
0 1 01
0 1 00
0 0 11
0 0 10
0 0 01
0 0 00
CPU_F, CPU1
(MHz)
133.3
124
150
140
105
110
115
120
100
133.3
112
103
66.8
83.3
75
124
PCI_F, 1:5 (MHz)
33.3 (CPU/4)
31 (CPU/4)
37.5 (CPU/4)
35 (CPU/4)
35 (CPU/3)
36.7 (CPU/3)
38.3 (CPU/3)
40 (CPU/3)
33.3 (CPU/3)
44.43 (CPU/3)
37.3 (CPU/3)
34.3 (CPU/3)
33.4 (CPU/2)
41.7 (CPU/2)
37.5 (CPU/2)
41.3 (CPU/3)
Logic Block Diagram
Pin Configuration
X1 XTAL
X2 OSC
PLL Ref Freq
I/O Pin
Control
Stop
Clock
Control
CLK_STOP#
PLL 1
Stop
Clock
Control
÷2,3,4
SDATA
SCLK
SDRAMIN
I2C
Logic
Stop
Clock
Control
PLL2
÷2
Stop
Clock
Control
VDDQ3
REF0/(PCI_STOP#)
REF1/FS2
VDDQ2
IOAPIC
VDDQ2
CPU1
CPU_F
VDDQ3
PCI_F/MODE
PCI1/FS3
PCI2
PCI3
PCI4
PCI5
VDDQ3
48MHz/FS0
24MHz/FS1
VDDQ3
SDRAM0:11
12
SDRAM_F
VDDQ3
REF0/(PCI_STOP#)
GND
X1
X2
VDDQ3
PCI_F/MODE
PCI1/FS3
GND
PCI2
PCI3
PCI4
PCI5
VDDQ3
SDRAMIN
GND
SDRAM11
SDRAM10
VDDQ3
SDRAM9
SDRAM8
GND
{I2C SDATA
SCLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48 VDDQ2
47 IOAPIC
46 REF1/FS2*
45 GND
44 CPU_F
43 CPU1
42 VDDQ2
41 CLK_STOP#
40 SDRAM_F
39 GND
38 SDRAM0
37 SDRAM1
36 VDDQ3
35 SDRAM2
34 SDRAM3
33 GND
32 SDRAM4
31 SDRAM5
30 VDDQ3
29 SDRAM6
28 SDRAM7
27 VDDQ3
26 48MHz/FS0*
25 24MHz/FS1*
Note:
1. Internal pull-up resistors should not be relied upon for setting
I/O pins HGH. Pin function with parentheses determined by
MODE pin resistor strapping. Unlike other I/O pins, input FS3
has an internal pull down resistor.
Intel is a registered trademark of Intel Corporation. I2C is a trademark of Philips Corporation.
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
November 2, 1999, rev. **
1 page  
PRELIMINARY
W144
Serial Data Interface
The W144 features a two-pin, serial data interface that can be
used to configure internal register settings that control partic-
ular device functions. Upon power-up, the W144 initializes with
default register settings, therefore the use of this serial data
interface is optional. The serial interface is write-only (to the
clock chip) and is the dedicated function of device pins SDATA
and SCLOCK. In motherboard applications, SDATA and
SCLOCK are typically driven by two logic outputs of the
Table 3. Serial Data Interface Control Functions Summary
chipset. Clock device register changes are normally made
upon system initialization, if any are required. The interface
can also be used during system operation for power manage-
ment functions. Table 3 summarizes the control functions of
the serial data interface.
Operation
Data is written to the W144 in eleven bytes of eight bits each.
Bytes are written in the order shown in Table 4.
Control Function
Clock Output Disable
CPU Clock Frequency
Selection
Spread Spectrum
Enabling
Output Three-state
(Reserved)
Description
Any individual clock output(s) can be disabled.
Disabled outputs are actively held LOW.
Provides CPU/PCI frequency selections through
software. Frequency is changed in a smooth and
controlled fashion.
Enables or disables spread spectrum clocking.
Common Application
Unused outputs are disabled to reduce EMI
and system power. Examples are clock
outputs to unused PCI slots.
For alternate microprocessors and power
management options. Smooth frequency
transition allows CPU frequency change
under normal system operation.
For EMI reduction.
Puts clock output into a high-impedance state.
Reserved function for future device revision or
production device testing.
Production PCB testing.
No user application. Register bit must be
written as 0.
Table 4. Byte Writing Sequence
Byte
Sequence
1
Byte Name
Slave Address
Bit Sequence
11010010
2 Command Code Don’t Care
3 Byte Count
Don’t Care
4 Data Byte 0
5 Data Byte 1
6 Data Byte 2
7 Data Byte 3
8 Data Byte 4
9 Data Byte 5
10 Data Byte 6
11 Data Byte 7
Refer to Table 5
Byte Description
Commands the W144 to accept the bits in Data Bytes 0–6 for internal
register configuration. Since other devices may exist on the same com-
mon serial data bus, it is necessary to have a specific slave address for
each potential receiver. The slave receiver address for the W144 is
11010010. Register setting will not be made if the Slave Address is not
correct (or is for an alternate slave receiver).
Unused by the W144, therefore bit values are ignored (“don’t care”).
This byte must be included in the data write sequence to maintain
proper byte allocation. The Command Code Byte is part of the standard
serial communication protocol and may be used when writing to anoth-
er addressed slave receiver on the serial data bus.
Unused by the W144, therefore bit values are ignored (“don’t care”).
This byte must be included in the data write sequence to maintain
proper byte allocation. The Byte Count Byte is part of the standard
serial communication protocol and may be used when writing to anoth-
er addressed slave receiver on the serial data bus.
The data bits in Data Bytes 0–7 set internal W144 registers that control
device operation. The data bits are only accepted when the Address
Byte bit sequence is 11010010, as noted above. For description of bit
control functions, refer to Table 5, Data Byte Serial Configuration Map.
5
5 Page 
PRELIMINARY
W144
SDRAM Clock Outputs, SDRAM, SDRAM0:11 (Lump Capacitance Test Load = 30 pF)
Parameter
tP
tH
tL
tR
tF
tPLH
tPHL
tD
tJC
tSK
tO
fST
Zo
Description
Period
High Time
Low Time
Output Rise Edge
Rate
Output Fall Edge
Rate
Prop Delay LH
Prop Delay HL
Duty Cycle
Jitter, Cycle-to-Cycle
Output Skew
CPU to PCI Clock
Skew
Frequency
Stabilization from
Power-up (cold start)
AC Output
Impedance
Test Condition/Comments
Measured on rising edge at 1.5V
Duration of clock cycle above 2.4V,
at min. edge rate (1.5 V/ns)
Duration of clock cycle below 0.4V,
at min. edge rate (1.5 V/ns)
Measured from 0.4V to 2.4V
Measured from 2.4V to 0.4V
Input edge rate faster than 1 V/ns
Input edge rate faster than 1 V/ns
Measured on rising and falling
edge at 1.5V, at min. sdge rate
(1.5 V/ns)
Measured on rising edge at 1.5V.
Maximum difference of cycle time
between two adjacent cycles.
Measured on rising edge at 1.5V
Covers all CPU/PCI outputs. Mea-
sured on rising edge at 1.5V. CPU
leads PCI output.
Assumes full supply voltage
reached within 1 ms from power-
up. Short cycles exist prior to fre-
quency stabilization.
Average value during switching
transition. Used for determining
series termination value.
CPU = 66.6 MHz
Min. Typ. Max.
30
5.6
5.3
1.5 4
1.5 4
15
15
45 55
250
250
1.5 4
3
30
CPU = 100 MHz
Min. Typ. Max. Unit
30 ns
3.3 ns
3.1 ns
1.5 4 V/ns
1.5 4 V/ns
1 5 ns
1 5 ns
45 55 %
250 ps
250 ps
1.5 4 ns
3 ms
30 Ω
11
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet W144.PDF ] | |
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