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Número de pieza | W40S11-23 | |
Descripción | Clock Buffer/Driver | |
Fabricantes | Cypress Semiconductor | |
Logotipo | ||
Hay una vista previa y un enlace de descarga de W40S11-23 (archivo pdf) en la parte inferior de esta página. Total 9 Páginas | ||
No Preview Available ! W40S11-23
Features
• Thirteen skew-controlled CMOS clock outputs
(SDRAM0:12)
• Supports three SDRAM DIMMs
• Ideal for high-performance systems designed around
Intel’s latest chip set
• I2C serial configuration interface
• Clock Skew between any two outputs is less than 250 ps
• 1- to 5-ns propagation delay
• DC to 133-MHz operation
• Single 3.3V supply voltage
• Low power CMOS design packaged in a 28-pin, 300-mil
SOIC (Small Outline Integrated Circuit)
Overview
The Cypress W40S11-23 is a low-voltage, thirteen-output
clock buffer. Output buffer impedance is approximately 15Ω,
which is ideal for driving SDRAM DIMMs.
Block Diagram
Clock Buffer/Driver
Key Specifications
Supply Voltages:........................................... VDD = 3.3V±5%
Operating Temperature:.................................... 0°C to +70°C
Input Threshold: .................................................. 1.5V typical
Maximum Input Voltage: .......................................VDD + 0.5V
Input Frequency:............................................... 0 to 133 MHz
BUF_IN to SDRAM0:12 Propagation Delay: ...... 1.0 to 5.0 ns
Output Edge Rate:.............................................. >1.5 V/ns
Output Clock Skew: .................................................. ±250 ps
Output Duty Cycle: .................................. 45/55% worst case
Output Impedance: ...............................................15Ω typical
Output Type: ................................................ CMOS rail-to-rail
Pin Configuration
SDATA
SCLOCK
Serial Port
Device Control
BUF_IN
SDRAM0
SDRAM1
SDRAM2
SDRAM3
SDRAM4
SDRAM5
SDRAM6
SDRAM7
SDRAM8
SDRAM9
SDRAM10
SDRAM11
SDRAM12
SOIC
VDD
SDRAM0
SDRAM1
GND
VDD
SDRAM2
SDRAM3
GND
BUF_IN
SDRAM4
SDRAM5
SDRAM12
VDD
SDATA[1]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28 VDD
27 SDRAM11
26 SDRAM10
25 GND
24 VDD
23 SDRAM9
22 SDRAM8
21 GND
20 VDD
19 SDRAM7
18 SDRAM6
17 GND
16
15
GSCNLDOCK[1]
Note:
1. Internal pull-up resistor of 250K on SDATA and SCLOCK inputs
(not CMOS level).
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
September 28, 1999 rev. **
1 page W40S11-23
Signaling Requirements
As shown in Figure 2, valid data bits are defined as stable logic
0 or 1 condition on the data line during a clock HIGH (logic 1)
pulse. A transitioning data line during a clock HIGH pulse may
be interpreted as a start or stop pulse (it will be interpreted as
a start or stop pulse if the start/stop timing parameters are
met).
A write sequence is initiated by a “start bit” as shown in Figure
3. A “stop bit” signifies that a transmission has ended.
As stated previously, the W40S11-23 sends an “acknowledge”
pulse after receiving eight data bits in each byte as shown in
Figure 4.
SDATA
SCLOCK
Valid
Data
Bit
Change
of Data Allowed
Figure 2. Serial Data Bus Valid Data Bit
SDATA
SCLOCK
Start
Bit
Figure 3. Serial Data Bus Start and Stop Bit
Stop
Bit
5
5 Page |
Páginas | Total 9 Páginas | |
PDF Descargar | [ Datasheet W40S11-23.PDF ] |
Número de pieza | Descripción | Fabricantes |
W40S11-23 | Clock Buffer/Driver | Cypress Semiconductor |
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