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PDF W6692 Data sheet ( Hoja de datos )
| Número de pieza | W6692 | |
| Descripción | PCI Bus ISDN S/T-Controller | |
| Fabricantes | Winbond | |
| Logotipo |  |
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Preliminary Data Sheet
W6692 PCI ISDN S/T-Controller
W6692
PCI Bus ISDN S/T-Controller
Data Sheet
-1 -
Publication Release Date: Sep 30, 1999
Revision 0.9
1 page  
Preliminary Data Sheet
W6692 PCI ISDN S/T-Controller
8.1.32 GCI Mode Control/Status Register GCR
Read/Write Address 7CH/1FH.......................................68
8.1.33 Peripheral Address Register XADDR Read/Write Address F4H/3DH ...............................................................69
8.1.34 Peripheral Data Register XDATA Read/Write Address F8H/3EH.....................................................................70
8.1.35 Serial EEPROM Control Register EPCTL Read/Write Address FCH/3FH ............................................................71
8.1.36 Monitor Receive Channel 1 Register MO1R Read Address 6DH/40H .................................................................71
8.1.37 Monitor Transmit Channel 1 MO1X Read/Write Address 71H/41H..................................................................72
8.1.38 Monitor Channel 1 Interrupt Register MO1I Read_clear Address 75H/42H ......................................................72
8.1.39 Monitor Channel 1 Control Register MO1C Read/Write Address 79H/43H ..........................................................72
8.1.40 GCI IC1 Receive Register IC1R Read Address 6EH/44H................................................................................73
8.1.41 GCI IC1 Transmit Register IC1X Read/Write Address 72H/45H.....................................................................73
8.1.42 GCI IC2 Receive Register IC2R Read Address 6FH/46H ................................................................................73
8.1.43 GCI IC2 Transmit Register IC2X Read/Write Address 73H/47H.....................................................................73
8.1.44 GCI CI1 Indication Register CI1R Read Address 7DH/48H ............................................................................74
8.1.45 GCI CI1 Command Register CI1X Read/Write Address 7EH/49H ..................................................................74
8.1.46 GCI Extended Interrupt Register GCI_EXIR Read_clear Address 76H/4AH ..........................................................74
8.1.47 GCI Extended Interrupt Mask Register GCI_EXIM Read/Write Address 7AH/4BH ...............................................75
8.2 B1 HDLC controler .........................................................................................................................................................75
8.2.1 B1_ch receive FIFO B1_RFIFO Read Address 80H/20H .....................................................................................76
8.2.2 B1_ch transmit FIFO B1_XFIFO Write Address 84H/21H .................................................................................76
8.2.3 B1_ch command register B1_CMDR Read/Write Address 88H/22H....................................................................77
8.2.4 B1_ch Mode Register B1_MODE Read/Write Address 8CH/23H ..........................................................................78
8.2.5 B1_ch Extended Interrupt Register B1_EXIR Read_clear Address 90H/24H............................................................79
8.2.6 B1_ch Extended Interrupt Mask Register B1_EXIM Read/Write Address 94H/25H .................................................80
8.2.7 B1_ch Status Register B1_STAR Read Address 98H/26H......................................................................................80
8.2.8 B1_ch Address Mask Register 1 B1_ADM1 Read/Write Address 9CH/27H...........................................................81
8.2.9 B1_ch Address Mask Register 2 B1_ADM2 Read/Write Address A0H/28H...........................................................81
8.2.10 B1_ch Address Register 1 B1_ADR1 Read/Write Address A4H/29H ...................................................................81
8.2.11 B1_ch Address Register 2 B1_ADR2 Read/Write Address A8H/2AH ..................................................................82
8.2.12 B1_ch Receive Frame Byte Count Low B1_RBCL Read Address ACH/2BH..........................................................82
8.2.13 B1_ch Receive Frame Byte Count High B1_RBCH Read Address B0H/2CH .........................................................82
8.2.14 B1_ch Transmit Idle Pattern B1_IDLE Read/Write Address B4H/2DH ..................................................................83
8.3 B2 HDLC controller ........................................................................................................................................................83
8.4 PCI Configuration Register.............................................................................................................................................84
8.4.1 Device/Vendor ID Register Read Address 00 H .................................................................................................85
8.4.2 Status/Command Register Read/Write Address 04H...........................................................................................85
8.4.3 Class Code/Revision ID Register Read Address 08H ..........................................................................................87
8.4.4 Header Type/Latency Timer Register Read Address 0CH ....................................................................................87
8.4.5 Base Address Register 0 Read/Write Address 10H............................................................................................88
8.4.6 Base Address Register 1 Read/Write Address 14H .............................................................................................89
8.4.7 Subsystem/Subsystem Vendor ID Register Read Address 2CH...........................................................................89
8.4.8 Interrupt Line Register Read/Write Address 3CH...............................................................................................90
8.4.9 Capability Pointer Read Address 34H ................................................................................................................90
8.4.10 Power Management Capability Read Address 40H ...........................................................................................91
8.4.11 Power Management Control/Status Read/Write Address 44H ...........................................................................92
9. ELECTRICAL CHARACTERISTICS...........................................................................................94
9.1 Absolute Maximum Rating..............................................................................................................................................94
-5 -
Publication Release Date: Sep 30, 1999
Revision 0.9
5 Page 
Preliminary Data Sheet
W6692 PCI ISDN S/T-Controller
I
OI I
1 OO
098
I
N
T
#
//
XX
WR
RD
BB
/
X
A
L
E
P PT
VVP P F P F E
D F S DR T C BC S
C S DDS D X XK CK T
L CDUDD D D1 K2 P
XX
II
V
S
S
D
V
D
D
D
X
T
A
L
2
X
T
A
L
1
S
X
2
S
X
1
N
T
I
N
1
N
T
I
N
0
V
D
D
A
RST#
VSSD
VDDD
CLK
VSSB
VDDB
81
82
8
0
7
9
77
87
7
6
7
5
7
4
77
32
77
10
6
9
66
87
6
6
6
5
6
4
6
3
6
2
66
10
5
9
55
87
5
6
5
5
5
4
5
3
5
2
5
1
50
49
83 48
84 47
85 46
86
87
W6692
45
44
88
89
ISDN-PCI
43
42
90 41
91 40
92 39
93 38
94 37
95 36
96 35
97 34
98 33
99
100
1
2
34
5
67
8
9
11
01
1
2
11
34
1
5
1
6
1
7
1
8
1
9
2
0
2
1
2
2
22
34
22
56
2
7
22
89
3
0
32
31
SR2
SR1
VSSA
AD0
AD1
AD2
AD3
VDDB
VSSB
AD4
AD5
AD6
AD7
RD#
VDDB
VSSB
I I I I VV
O O OOS D
0 1 23S D
/ / / / BB
X X XX
A A AA
D D DD
0 1 23
CA VV T W
S
#
L
SD
SD
OR
U#
E DD T
2
II II
OO OO
45 67
// //
XX XX
AA AA
DD DD
45 67
FIG.3.2 W6692 PIN CONFIGURATION - INTEL BUS MODE
-11 -
Publication Release Date: Sep 30, 1999
Revision 0.9
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet W6692.PDF ] | |
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