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PDF 74LCXH162373MTD Data sheet ( Hoja de datos )
| Número de pieza | 74LCXH162373MTD | |
| Descripción | Low Voltage 16-Bit Transparent Latch with Bushold and 26 Series Resistor Outputs | |
| Fabricantes | Fairchild Semiconductor | |
| Logotipo |  |
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February 2001
Revised March 2002
74LCXH162373
Low Voltage 16-Bit Transparent Latch
with Bushold and 26Ω Series Resistor Outputs
General Description
The LCXH162373 contains sixteen non-inverting latches
with 3-STATE outputs and is intended for bus oriented
applications. The device is byte controlled. The flip-flops
appear transparent to the data when the Latch Enable (LE)
is HIGH. When LE is LOW, the data that meets the setup
time is latched. Data appears on the bus when the Output
Enable (OE) is LOW. When OE is HIGH, the outputs are in
a high impedance state.
The LCXH162373 is designed for low voltage (2.5V or
3.3V) VCC applications with capability of interfacing to a 5V
signal environment. The 26Ω series resistor helps reduce
output overshoot and undershoot.
The LCXH162373 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintain-
ing CMOS low power dissipation.
The LCXH162373 data inputs include active bushold cir-
cuitry, eliminating the need for external pull-up resistors to
hold unused or floating data inputs at a valid logic level.
Features
s 5V tolerant control inputs and outputs
s 2.3V–3.6V VCC specifications provided
s Equivalent 26Ω series resistors on outputs
s Bushold on inputs eliminates the need for external
pull-up/pull-down resistors
s 6.2 ns tPD max (VCC = 3.3V), 20 µA ICC max
s Power down high impedance inputs and outputs
s ±12 mA output drive (VCC = 3.0V)
s Implements patented noise/EMI reduction circuitry
s Latch-up performance exceeds 500 mA
s ESD performance:
Human body model > 2000V
Machine model > 200V
s Also packaged in plastic Fine-Pitch Ball Grid Array
(FBGA) (Preliminary)
Ordering Code:
Order Number
Package
Number
Package Description
74LCXH162373GX
(Note 1)
BGA54A 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
(Preliminary) [TAPE and REEL]
74LCXH162373MEA
MS48A
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
[RAIL]
74LCXH162373MEX
MS48A
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
[TAPE and REEL]
74LCXH162373MTD
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
[RAIL]
74LCXH162373MTX
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
[TAPE and REEL]
Note 1: BGA package available in Tape and Reel only.
Logic Symbol
© 2002 Fairchild Semiconductor Corporation DS500445
www.fairchildsemi.com
1 page  
DC Electrical Characteristics (Continued)
Symbol
Parameter
Conditions
II(HOLD)
Bushold Input Minimum
Drive Hold Current
II(OD)
Bushold Input Over-Drive
Current to Change State
VIN = 0.7V
VIN = 1.7V
VIN = 0.8V
VIN = 2.0V
(Note 6)
(Note 7)
(Note 6)
(Note 7)
IOZ 3-STATE Output Leakage
IOFF Power-Off Leakage Current
ICC Quiescent Supply Current
∆ICC
Increase in ICC per Input
Note 5: Outputs disabled or 3-STATE only.
0 ≤ VO ≤ 5.5V
VI = VIH or VIL
VO = VCC
VI = VCC or GND
3.6V ≤ VO ≤ 5.5V (Note 5)
VIH = VCC −0.6V
Note 6: An external driver must source at least the specified current to switch from LOW-to-HIGH.
Note 7: An external driver must sink at least the specified current to switch from HIGH-to-LOW.
VCC
(V)
2.3
3.0
2.7
3.6
2.3 − 3.6
0
2.3 − 3.6
2.3 − 3.6
2.3 − 3.6
TA = −40°C to +85°C
Min Max
45
−45
75
−75
300
−300
450
−450
±5.0
10
20
±20
500
Units
µA
µA
µA
µA
µA
µA
AC Electrical Characteristics
TA = −40°C to +85°C, RL = 500Ω
Symbol
Parameter
VCC = 3.3V ± 0.3V
CL = 50 pF
VCC = 2.7V
CL = 50 pF
VCC = 2.5V ± 0.2V
CL = 30 pF
Units
Min Max Min Max Min Max
tPHL Propagation Delay
tPLH
In to On
1.5 6.2 1.5 6.7 1.5 7.4
ns
1.5 6.2 1.5 6.7 1.5 7.4
tPHL Propagation Delay
tPLH
LE to On
1.5 6.3 1.5 7.2 1.5 7.6
ns
1.5 6.3 1.5 7.2 1.5 7.6
tPZL
tPZH
Output Enable Time
1.5 6.9 1.5 7.3 1.5 9.0
ns
1.5 6.9 1.5 7.3 1.5 9.0
tPLZ
tPHZ
Output Disable Time
1.5 6.0 1.5 6.3 1.5 7.2
ns
1.5 6.0 1.5 6.3 1.5 7.2
tS Setup Time, In to LE
2.5 2.5 3.0 ns
tH Hold Time, In to LE
1.5 1.5 2.0 ns
tW LE Pulse Width
3.0 3.0 3.5 ns
tOSHL
tOSLH
Output to Output Skew (Note 8)
1.0
1.0
ns
Note 8: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH). Parameter guaranteed by design.
5 www.fairchildsemi.com
5 Page 
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Package Number MTD48
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
11 www.fairchildsemi.com
11 Page | ||
| Páginas | Total 11 Páginas | |
| PDF Descargar | [ Datasheet 74LCXH162373MTD.PDF ] | |
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