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PDF MC-4516CD641PS-A80 Data sheet ( Hoja de datos )
| Número de pieza | MC-4516CD641PS-A80 | |
| Descripción | 16M-WORD BY 64-BIT SYNCHRONOUS DYNAMIC RAM MODULE SO DIMM | |
| Fabricantes | NEC | |
| Logotipo |  |
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DATA SHEET
MOS INTEGRATED CIRCUIT
MC-4516CD641ES, 4516CD641PS
16M-WORD BY 64-BIT
SYNCHRONOUS DYNAMIC RAM MODULE (SO DIMM)
Description
The MC-4516CD641ES and MC-4516CD641PS are 16,777,216 words by 64 bits synchronous dynamic RAM
module (Small Outline DIMM) on which 8 pieces of 128M SDRAM: µPD45128163 are assembled.
These modules provide high density and large quantities of memory in a small space without utilizing the surface-
mounting technology on the printed circuit board.
Decoupling capacitors are mounted on power supply line for noise reduction.
Features
• 16,777,216 words by 64 bits organization
• Clock frequency and access time from CLK
Part number
/CAS latency
Clock frequency (MAX.) Access time from CLK (MAX.)
MC-4516CD641ES-A80
MC-4516CD641ES-A10
5 MC-4516CD641PS-A80
5 MC-4516CD641PS-A10
CL = 3
CL = 2
CL = 3
CL = 2
CL = 3
CL = 2
CL = 3
CL = 2
125 MHz
100 MHz
100 MHz
77 MHz
125 MHz
100 MHz
100 MHz
77 MHz
6 ns
6 ns
6 ns
7 ns
6 ns
6 ns
6 ns
7 ns
• Fully Synchronous Dynamic RAM, with all signals referenced to a positive clock edge
• Pulsed interface
• Possible to assert random column address in every cycle
• Quad internal banks controlled by BA0, BA1 (Bank Select)
• Programmable burst-length (1, 2, 4, 8 and Full Page)
• Programmable wrap sequence (Sequential / Interleave)
• Programmable /CAS latency (2, 3)
• Automatic precharge and controlled precharge
• CBR (Auto) refresh and self refresh
• Single 3.3 V ±0.3 V power supply
• LVTTL compatible
• 4,096 refresh cycles/64 ms
• Burst termination by Burst Stop command and Precharge command
• 144-pin small outline dual in-line memory module (Pin pitch = 0.8 mm)
• Unbuffered type
• Serial PD
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. M14014EJ5V0DS00 (5th edition)
Date Published February 2000 NS CP(K)
Printed in Japan
The mark • shows major revised points.
©
1999
1 page  
MC-4516CD641ES, 4516CD641PS
Electrical Specifications
• All voltages are referenced to VSS (GND).
• After power up, wait more than 100 µs and then, execute power on sequence and CBR (Auto) refresh before proper
device operation is achieved.
Absolute Maximum Ratings
Parameter
Symbol
Condition
Rating
Unit
Voltage on power supply pin relative to GND
Voltage on input pin relative to GND
Short circuit output current
Power dissipation
Operating ambient temperature
Storage temperature
VCC
VT
IO
PD
TA
Tstg
–0.5 to +4.6
–0.5 to +4.6
50
8
0 to +70
–55 to +125
V
V
mA
W
°C
°C
Caution
Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Recommended Operating Conditions
Parameter
Symbol
Supply voltage
VCC
High level input voltage
VIH
Low level input voltage
VIL
Operating ambient temperature
TA
Condition
MIN.
3.0
2.0
–0.3
0
TYP. MAX. Unit
3.3 3.6
V
VCC + 0.3 V
+ 0.8
V
70 °C
Capacitance (TA = 25 °C, f = 1 MHz)
Parameter
Input capacitance
Data input/output capacitance
Symbol
Test condition
CI1 A0 - A11, BA0(A13), BA1(A12),
/RAS, /CAS, /WE
CI2 CLK0, CLK1
CI3 CKE0, CKE1
CI4 /CS0, /CS1
CI5 DQMB0 - DQMB7
CI/O DQ0 - DQ63
MIN.
30
23
18
18
7
9
TYP.
MAX.
60
37
30
30
14
18
Unit
pF
pF
Data Sheet M14014EJ5V0DS00
5
5 Page 
MC-4516CD641ES, 4516CD641PS
Byte No.
Function Described
32 Command and address
-A80
signal setup time
-A10
33 Command and address
-A80
signal hold time
-A10
34 Data signal input setup time -A80
-A10
35 Data signal input hold time
-A80
-A10
36-61
62 SPD revision
-A80
-A10
63 Checksum
-A80
for bytes 0 - 62
-A10
64-71 Manufacture’s JEDEC ID code
72 Manufacturing location
73-90 Manufacture’s P/N
91-92 Revision code
93-94 Manufacturing date
95-98 Assembly serial number
99-125 Mfg specific
126 Intel specification frequency -A80
-A10
127 Intel specification /CAS
-A80
latency support
-A10
(2/2)
Hex Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Notes
20H 0 0 1 0 0 0 0 0 2 ns
20H 0 0 1 0 0 0 0 0 2 ns
10H 0 0 0 1 0 0 0 0 1 ns
10H 0 0 0 1 0 0 0 0 1 ns
20H 0 0 1 0 0 0 0 0 2 ns
20H 0 0 1 0 0 0 0 0 2 ns
10H 0 0 0 1 0 0 0 0 1 ns
10H 0 0 0 1 0 0 0 0 1 ns
00H 0 0 0 0 0 0 0 0
12H 0 0 0 1 0 0 1 0 1.2 A
12H 0 0 0 1 0 0 1 0 1.2 A
E8H 1 1 1 0 1 0 0 0
4EH 0 1 1 0 1 1 1 0
64H 0 1 1 0 0 1 0 0 100 MHz
64H 0 1 1 0 0 1 0 0 100 MHz
C7H 1 1 0 0 0 1 1 1
C5H 1 1 0 0 0 1 0 1
Timing Chart
Refer to the SYNCHRONOUS DRAM MODULE TIMING CHART Information (M13348E).
Data Sheet M14014EJ5V0DS00
11
11 Page | ||
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