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PDF MC-4564EC726 Data sheet ( Hoja de datos )
| Número de pieza | MC-4564EC726 | |
| Descripción | 64 M-WORD BY 72-BIT SYNCHRONOUS DYNAMIC RAM MODULE REGISTERED TYPE | |
| Fabricantes | NEC | |
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DATA SHEET
MOS INTEGRATED CIRCUIT
MC-4564EC726
64 M-WORD BY 72-BIT SYNCHRONOUS DYNAMIC RAM MODULE
REGISTERED TYPE
Description
The MC-4564EC726 is a 67,108,864 words by 72 bits synchronous dynamic RAM module on which 36 pieces of
128 M SDRAM: µPD45128441 are assembled.
These modules provide high density and large quantities of memory in a small space without utilizing the surface-
mounting technology on the printed circuit board.
Decoupling capacitors are mounted on power supply line for noise reduction.
Features
• 67,108,864 words by 72 bits organization (ECC type)
• Clock frequency and access time from CLK
Part number
/CAS latency
Clock frequency
(MAX.)
Access time from CLK
(MAX.)
Module type
MC-4564EC726EFB-A80
CL = 3
125 MHz
6 ns PC100 Registered DIMM
CL = 2
100 MHz
6 ns Rev. 1.2 Compliant
MC-4564EC726EFB-A10
CL = 3
100 MHz
6 ns
5 MC-4564EC726PFB-A80
CL = 2
CL = 3
77 MHz
125 MHz
7 ns
6 ns
CL = 2
100 MHz
6 ns
5 MC-4564EC726PFB-A10
CL = 3
100 MHz
6 ns
CL = 2
77 MHz
7 ns
• Fully Synchronous Dynamic RAM, with all signals referenced to a positive clock edge
• Pulsed interface
• Possible to assert random column address in every cycle
• Quad internal banks controlled by BA0 and BA1 (Bank Select)
• Programmable burst-length (1, 2, 4, 8 and Full Page)
• Programmable wrap sequence (Sequential / Interleave)
• Programmable /CAS latency (2, 3)
• Automatic precharge and controlled precharge
• CBR (Auto) refresh and self refresh
• All DQs have 10 Ω ± 10 % of series resistor
• Single 3.3 V ± 0.3 V power supply
• LVTTL compatible
• 4,096 refresh cycles / 64 ms
• Burst termination by Burst Stop command and Precharge command
• 168-pin dual in-line memory module (Pin pitch = 1.27 mm)
• Registered type
• Serial PD
• Stacked monolithic technology
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. M14460EJ2V0DS00 (2nd edition)
Date Published February 2000 NS CP(K)
Printed in Japan
The mark 5 shows major revised points.
©
1999
1 page  
MC-4564EC726
Block Diagram
REGE
10 kΩ
A1
A3
A5
A7
A9
/RAS
/CAS
BA0
/CS1
DQMB4
DQMB5
A0
A2
A4
A6
A8
A10
/WE
BA0
/CS0
DQMB0
DQMB1
A11
BA1
CKE0
/CS2
/CS3
DQMB2
DQMB3
DQMB6
DQMB7
Register 1
/LE
Register 2
/LE
Register 3
/LE
R1A1: D0-D4, D9-D12, D18-D22, D27-D30
R2A1: D5-D8, D13-D17, D23-D26, D31-D35
R1A3: D0-D4, D9-D12, D18-D22, D27-D30
R2A3: D5-D8, D13-D17, D23-D26, D31-D35
R1A5: D0-D4, D9-D12, D18-D22, D27-D30
R2A5: D5-D8, D13-D17, D23-D26, D31-D35
R1A7: D0-D4, D9-D12, D18-D22, D27-D30
R2A7: D5-D8, D13-D17, D23-D26, D31-D35
R1A9: D0-D4, D9-D12, D18-D22, D27-D30
R2A9: D5-D8, D13-D17, D23-D26, D31-D35
R1RAS: D0-D4, D9-D12, D18-D22, D27-D30
R2RAS: D5-D8, D13-D17, D23-D26, D31-D35
R1CAS: D0-D4, D9-D12, D18-D22, D27-D30
R2CAS: D5-D8, D13-D17, D23-D26, D31-D35
R1BA0: D0-D4, D9-D12, D18-D22, D27-D30
RCS1
RDQMB4
RDQMB5
(2/2)
R1A0: D0-D4, D9-D12, D18-D22, D27-D30
R2A0: D5-D8, D13-D17, D23-D26, D31-D35
R1A2: D0-D4, D9-D12, D18-D22, D27-D30
R2A2: D5-D8, D13-D17, D23-D26, D31-D35
R1A4: D0-D4, D9-D12, D18-D22, D27-D30
R2A4: D5-D8, D13-D17, D23-D26, D31-D35
R1A6: D0-D4, D9-D12, D18-D22, D27-D30
R2A6: D5-D8, D13-D17, D23-D26, D31-D35
R1A8: D0-D4, D9-D12, D18-D22, D27-D30
R2A8: D5-D8, D13-D17, D23-D26, D31-D35
R1A10: D0-D4, D9-D12, D18-D22, D27-D30
R2A10: D5-D8, D13-D17, D23-D26, D31-D35
R1WE: D0-D4, D9-D12, D18-D22, D27-D30
R2WE: D5-D8, D13-D17, D23-D26, D31-D35
R2BA0: D5-D8, D13-D17, D23-D26, D31-D35
RCS0
RDQMB4
RDQMB5
R1A11: D0-D4, D9-D12, D18-D22, D27-D30
R2A11: D5-D8, D13-D17, D23-D26, D31-D35
R1BA1: D0-D4, D9-D12, D18-D22, D27-D30
R2BA1: D5-D8, D13-D17, D23-D26, D31-D35
R1CKE0: D0-D2, D9-D10, D18-D20, D27-D28
R2CKE0: D5-D6, D14-D15, D23-D24, D32-D33
R3CKE0: D3-D4, D11-D13, D21-D22, D29-D31
R4CKE0: D7-D8, D16-D17, D23-D24, D34-D35
RCS2
RCS3
RDQMB2
RDQMB3
RDQMB6
RDQMB7
Remarks 1. The value of all resistors of DQs is 10 Ω.
2. D0 – D35: µPD45128441 (8M words × 4 bits × 4 banks)
3. REGE ≤ VIL: Buffer mode
REGE ≥ VIH: Register mode
4. Register: HD74ALVC16835
PLL: HD74CDC2510B
Data Sheet M14460EJ2V0DS00
5
5 Page 
MC-4564EC726
Serial PD
Byte No.
Function Described
0 Defines the number of bytes written into
serial PD memory
1 Total number of bytes of serial PD memory
2 Fundamental memory type
3 Number of rows
4 Number of columns
5 Number of banks
6 Data width
7 Data width (continued)
8 Voltage interface
9 CL = 3 Cycle time
-A80
-A10
10 CL = 3 Access time
-A80
-A10
11 DIMM configuration type
12 Refresh rate/type
13 SDRAM width
14 Error checking SDRAM width
15 Minimum clock delay
16 Burst length supported
17 Number of banks on each SDRAM
18 /CAS latency supported
19 /CS latency supported
20 /WE latency supported
21 SDRAM module attributes
22 SDRAM device attributes : General
23 CL = 2 Cycle time
-A80
-A10
24 CL = 2 Access time
-A80
-A10
25-26
27 tRP(MIN.)
-A80
-A10
28 tRRD(MIN.)
-A80
-A10
29 tRCD(MIN.)
-A80
-A10
30 tRAS(MIN.)
-A80
-A10
31 Module bank density
(1/2)
Hex Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Notes
80H 1 0 0 0 0 0 0 0 128 bytes
08H 0 0 0 0 1 0 0 0 256 bytes
04H 0 0 0 0 0 1 0 0 SDRAM
0CH 0 0 0 0 1 1 0 0 12 rows
0BH 0 0 0 0 1 0 1 1 11 columns
02H 0 0 0 0 0 0 1 0 2 bank
48H 0 1 0 0 1 0 0 0 72 bits
00H 0 0 0 0 0 0 0 0 0
01H 0 0 0 0 0 0 0 1 LVTTL
80H 1 0 0 0 0 0 0 0 8 ns
A0H 1 0 1 0 0 0 0 0 10 ns
60H 0 1 1 0 0 0 0 0 6 ns
60H 0 1 1 0 0 0 0 0 6 ns
02H 0 0 0 0 0 0 1 0 ECC
80H 1 0 0 0 0 0 0 0 Normal
04H 0 0 0 0 0 1 0 0 x4
04H 0 0 0 0 0 1 0 0 x4
01H 0 0 0 0 0 0 0 1 1 clock
8FH 1 0 0 0 1 1 1 1 1, 2, 4, 8, F
04H 0 0 0 0 0 1 0 0 4 banks
06H 0 0 0 0 0 1 1 0 2, 3
01H 0 0 0 0 0 0 0 1 0
01H 0 0 0 0 0 0 0 1 0
1FH 0 0 0 1 1 1 1 1 Registered
0EH 0 0 0 0 1 1 1 0
A0H 1 0 1 0 0 0 0 0 10 ns
D0H 1 1 0 1 0 0 0 0 13 ns
60H 0 1 1 0 0 0 0 0 6 ns
70H 0 1 1 1 0 0 0 0 7 ns
00H 0 0 0 0 0 0 0 0
14H 0 0 0 1 0 1 0 0 20 ns
14H 0 0 0 1 0 1 0 0 20 ns
10H 0 0 0 1 0 0 0 0 16 ns
14H 0 0 0 1 0 1 0 0 20 ns
14H 0 0 0 1 0 1 0 0 20 ns
14H 0 0 0 1 0 1 0 0 20 ns
30H 0 0 1 1 0 0 0 0 48 ns
32H 0 0 1 1 0 0 1 0 50 ns
40H 0 1 0 0 0 0 0 0 256M bytes
Data Sheet M14460EJ2V0DS00
11
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet MC-4564EC726.PDF ] | |
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