|
|
PDF MC-4564EC727 Data sheet ( Hoja de datos )
| Número de pieza | MC-4564EC727 | |
| Descripción | 64M-WORD BY 72-BIT SYNCHRONOUS DYNAMIC RAM MODULE REGISTERED TYPE | |
| Fabricantes | NEC | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de MC-4564EC727 (archivo pdf) en la parte inferior de esta página. Total 16 Páginas | ||
|
No Preview Available !
DATA SHEET
MOS INTEGRATED CIRCUIT
MC-4564EC727
64M-WORD BY 72-BIT SYNCHRONOUS DYNAMIC RAM MODULE
REGISTERED TYPE
Description
The MC-4564EC727 is a 67,108,864 words by 72 bits synchronous dynamic RAM module on which 36 pieces of
128 M SDRAM: µPD45128441 are assembled.
This module provides high density and large quantities of memory in a small space without utilizing the surface-
mounting technology on the printed circuit board.
Decoupling capacitors are mounted on power supply line for noise reduction.
Features
• 67,108,864 words by 72 bits organization (ECC type)
• Clock frequency and access time from CLK
Part number
/CAS latency
Clock frequency
(MAX.)
Access time from CLK
(MAX.)
Module type
MC-4564EC727EF-A75
5
5 MC-4564EC727PF-A75
CL = 3
CL = 2
CL = 3
CL = 2
133 MHz
100 MHz
133 MHz
100 MHz
5.4 ns
6.0 ns
5.4 ns
6.0 ns
PC133 Registered DIMM
Rev. 1.0 Compliant
• Fully Synchronous Dynamic RAM, with all signals referenced to a positive clock edge
• Pulsed interface
• Possible to assert random column address in every cycle
• Quad internal banks controlled by BA0 and BA1 (Bank Select)
• Programmable burst-length (1, 2, 4, 8 and Full Page)
• Programmable wrap sequence (Sequential / Interleave)
5 • Programmable /CAS latency (2, 3)
• Automatic precharge and controlled precharge
• CBR (Auto) refresh and self refresh
• All DQs have 10 Ω ± 10 % of series resistor
• Single 3.3 V ±0.3 V power supply
• LVTTL compatible
• 4,096 refresh cycles/64 ms
• Burst termination by Burst Stop command and Precharge command
• 168-pin dual in-line memory module (Pin pitch = 1.27 mm)
• Registered type
• Serial PD
• Stacked monolithic technology
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. M14461EJ2V0DS00 (2nd edition)
Date Published February 2000 NS CP(K)
Printed in Japan
The mark 5 shows major revised points.
©
1999
1 page  
MC-4564EC727
REGE
10 kΩ
A1
A3
A5
A7
A9
/RAS
/CAS
BA0
/CS1
DQMB4
DQMB5
A0
A2
A4
A6
A8
A10
/WE
BA0
/CS0
DQMB0
DQMB1
A11
BA1
CKE0
/CS2
/CS3
DQMB2
DQMB3
DQMB6
DQMB7
Register 1
/LE
Register 2
/LE
Register 3
/LE
R1A1: D0-D4, D9-D12, D18-D22, D27-D30
R2A1: D5-D8, D13-D17, D23-D26, D31-D35
R1A3: D0-D4, D9-D12, D18-D22, D27-D30
R2A3: D5-D8, D13-D17, D23-D26, D31-D35
R1A5: D0-D4, D9-D12, D18-D22, D27-D30
R2A5: D5-D8, D13-D17, D23-D26, D31-D35
R1A7: D0-D4, D9-D12, D18-D22, D27-D30
R2A7: D5-D8, D13-D17, D23-D26, D31-D35
R1A9: D0-D4, D9-D12, D18-D22, D27-D30
R2A9: D5-D8, D13-D17, D23-D26, D31-D35
R1RAS: D0-D4, D9-D12, D18-D22, D27-D30
R2RAS: D5-D8, D13-D17, D23-D26, D31-D35
R1CAS: D0-D4, D9-D12, D18-D22, D27-D30
R2CAS: D5-D8, D13-D17, D23-D26, D31-D35
R1BA0: D0-D4, D9-D12, D18-D22, D27-D30
RCS1
RDQMB4
RDQMB5
(2/2)
R1A0: D0-D4, D9-D12, D18-D22, D27-D30
R2A0: D5-D8, D13-D17, D23-D26, D31-D35
R1A2: D0-D4, D9-D12, D18-D22, D27-D30
R2A2: D5-D8, D13-D17, D23-D26, D31-D35
R1A4: D0-D4, D9-D12, D18-D22, D27-D30
R2A4: D5-D8, D13-D17, D23-D26, D31-D35
R1A6: D0-D4, D9-D12, D18-D22, D27-D30
R2A6: D5-D8, D13-D17, D23-D26, D31-D35
R1A8: D0-D4, D9-D12, D18-D22, D27-D30
R2A8: D5-D8, D13-D17, D23-D26, D31-D35
R1A10: D0-D4, D9-D12, D18-D22, D27-D30
R2A10: D5-D8, D13-D17, D23-D26, D31-D35
R1WE: D0-D4, D9-D12, D18-D22, D27-D30
R2WE: D5-D8, D13-D17, D23-D26, D31-D35
R2BA0: D5-D8, D13-D17, D23-D26, D31-D35
RCS0
RDQMB4
RDQMB5
R1A11: D0-D4, D9-D12, D18-D22, D27-D30
R2A11: D5-D8, D13-D17, D23-D26, D31-D35
R1BA1: D0-D4, D9-D12, D18-D22, D27-D30
R2BA1: D5-D8, D13-D17, D23-D26, D31-D35
R1CKE0: D0-D2, D9-D10, D18-D20, D27-D28
R2CKE0: D5-D6, D14-D15, D23-D24, D32-D33
R3CKE0: D3-D4, D11-D13, D21-D22, D29-D31
R4CKE0: D7-D8, D16-D17, D23-D24, D34-D35
RCS2
RCS3
RDQMB2
RDQMB3
RDQMB6
RDQMB7
Remarks 1. The value of all resistors of DQs is 10 Ω.
2. D0 – D35: µPD45128441 (8 M words × 4 bits × 4 banks)
3. REGE ≤ VIL: Buffer mode
REGE ≥ VIH: Register mode
4. Register: SN74AVC16834DGG
5 PLL: HD74CDCF2510B, IDTCSP2510C
Data Sheet M14461EJ2V0DS00
5
5 Page 
MC-4564EC727
Serial PD
(1/2)
Byte No.
Function Described
Hex Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Notes
Defines the number of bytes written into
0 80H 1 0 0 0 0 0 0 0 128 bytes
serial PD memory
1 Total number of bytes of serial PD memory 08H 0 0 0 0 1 0 0 0 256 bytes
2 Fundamental memory type
04H 0 0 0 0 0 1 0 0 SDRAM
3 Number of rows
0CH 0 0 0 0 1 1 0 0 12 rows
4 Number of columns
0BH 0 0 0 0 1 0 1 1 11 columns
5 Number of module banks
02H 0 0 0 0 0 0 1 0 2 banks
6 Data width
48H 0 1 0 0 1 0 0 0 72 bits
7 Data width (continued)
00H 0 0 0 0 0 0 0 0 0
8 Voltage interface
01H 0 0 0 0 0 0 0 1 LVTTL
9 CL = 3 Cycle time
-A75 75H 0 1 1 1 0 1 0 1 7.5 ns
10 CL = 3 Access time
-A75 54H 0 1 0 1 0 1 0 0 5.4 ns
11 DIMM configuration type
02H 0 0 0 0 0 0 1 0 ECC
12 Refresh rate/type
80H 1 0 0 0 0 0 0 0 Normal
13 SDRAM width
04H 0 0 0 0 0 1 0 0 x4
14 Error checking SDRAM width
04H 0 0 0 0 0 1 0 0 x4
15 Minimum clock delay
01H 0 0 0 0 0 0 0 1 1 clock
16 Burst length supported
8FH 1 0 0 0 1 1 1 1 1, 2, 4, 8, F
17 Number of banks on each SDRAM
5 18 /CAS latency supported
04H 0 0 0 0 0 1 0 0 4 banks
06H 0 0 0 0 0 1 1 0 2, 3
19 /CS latency supported
01H 0 0 0 0 0 0 0 1 0
20 /WE latency supported
01H 0 0 0 0 0 0 0 1 0
21 SDRAM module attributes
1FH 0 0 0 1 1 1 1 1 Registered
22 SDRAM device attributes: General
0EH 0 0 0 0 1 1 1 0
5 23 CL = 2 Cycle time
-A75 A0H 0 0 0 0 1 0 1 0 10 ns
5 24 CL = 2 Access time
-A75 60H 0 1 1 0 0 0 0 0 6 ns
25-26
00H 0 0 0 0 0 0 0 0
5 27 tRP(MIN.)
28 tRRD(MIN.)
5 29 tRCD(MIN.)
30 tRAS(MIN.)
31 Module bank density
-A75 14H 0 0 0 1 0 1 0 0 20 ns
-A75 0FH 0 0 0 0 1 1 1 1 15 ns
-A75 14H 0 0 0 1 0 1 0 0 20 ns
-A75 2DH 0 0 1 0 1 1 0 1 45 ns
40H 0 1 0 0 0 0 0 0 256M bytes
Data Sheet M14461EJ2V0DS00
11
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet MC-4564EC727.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| MC-4564EC726 | 64 M-WORD BY 72-BIT SYNCHRONOUS DYNAMIC RAM MODULE REGISTERED TYPE | NEC |
| MC-4564EC727 | 64M-WORD BY 72-BIT SYNCHRONOUS DYNAMIC RAM MODULE REGISTERED TYPE | NEC |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |