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PDF MC-458CB64PSB Data sheet ( Hoja de datos )
| Número de pieza | MC-458CB64PSB | |
| Descripción | 8M-WORD BY 64-BIT SYNCHRONOUS DYNAMIC RAM MODULE SO DIMM | |
| Fabricantes | NEC | |
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DATA SHEET
MOS INTEGRATED CIRCUIT
MC-458CB64ESB, 458CB64PSB
8M-WORD BY 64-BIT
SYNCHRONOUS DYNAMIC RAM MODULE (SO DIMM)
Description
The MC-458CB64ESB and MC-458CB64PSB are 8,388,608 words by 64 bits synchronous dynamic RAM module
(Small Outline DIMM) on which 4 pieces of 128M SDRAM: µPD45128163 are assembled.
These modules provide high density and large quantities of memory in a small space without utilizing the surface-
mounting technology on the printed circuit board.
Decoupling capacitors are mounted on power supply line for noise reduction.
Features
• 8,388,608 words by 64 bits organization
• Clock frequency and access time from CLK
Part number
/CAS Latency
Clock frequency
(MAX.)
MC-458CB64ESB-A10B
CL = 3
100 MHz
5 MC-458CB64PSB-A10B
CL = 2
CL = 3
CL = 2
67 MHz
100 MHz
67 MHz
• Fully Synchronous Dynamic RAM, with all signals referenced to a positive clock edge
• Pulsed interface
• Possible to assert random column address in every cycle
• Quad internal banks controlled by BA0 and BA1 (Bank Select)
• Programmable burst-length (1, 2, 4, 8 and Full Page)
• Programmable wrap sequence (Sequential / Interleave)
• Programmable /CAS latency (2, 3)
• Automatic precharge and controlled precharge
• CBR (Auto) refresh and self refresh
• Single +3.3 V ± 0.3 V power supply
• LVTTL compatible
• 4,096 refresh cycles/64 ms
• Burst termination by Burst Stop command and Precharge command
• 144-pin small outline dual in-line memory module (Pin pitch = 0.8 mm)
• Unbuffered type
• Serial PD
Access time from CLK
(MIN.)
7 ns
8 ns
7 ns
8 ns
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. M12263EJAV0DS00 (10th edition)
Date Published February 2000 NS CP(K)
Printed in Japan
The mark • shows major revised points.
©
1996
1 page  
MC-458CB64ESB, 458CB64PSB
Electrical Specifications
• All voltages are referenced to VSS (GND).
• After power up, wait more than 100 µs and then, execute power on sequence and CBR (Auto) refresh before proper
device operation is achieved.
Absolute Maximum Ratings
Parameter
Symbol
Condition
Rating
Unit
Voltage on power supply pin relative to GND
Voltage on input pin relative to GND
Short circuit output current
Power dissipation
Operating ambient temperature
Storage temperature
VCC
VT
IO
PD
TA
Tstg
–0.5 to +4.6
–0.5 to +4.6
50
4
0 to +70
–55 to +125
V
V
mA
W
°C
°C
Caution
Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Recommended Operating Conditions
Parameter
Supply voltage
High level input voltage
Low level input voltage
Operating ambient temperature
Symbol
VCC
VIH
VIL
TA
Condition
MIN.
3.0
2.0
–0.3
0
TYP. MAX. Unit
3.3 3.6
V
VCC + 0.3 V
+ 0.8
V
70 °C
Capacitance (TA = 25 °C, f = 1 MHz)
Parameter
Input capacitance
Data input/output capacitance
Symbol
Test condition
MIN.
CI1 A0 - A11, BA0 (A13), BA1 (A12),
/RAS, /CAS, /WE
CI2 CLK0
CI3 CKE0
CI4 /CS0
CI5 DQMB0 -DQMB7
CI/O DQ0 - DQ63
TYP.
MAX.
30
30
30
30
10
10
Unit
pF
pF
Data Sheet M12263EJAV0DS00
5
5 Page 
MC-458CB64ESB, 458CB64PSB
(2/2)
Byte No.
Function Described
Hex Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Notes
31 Module bank density
10H 0 0 0 1 0 0 0 0 64 M bytes
32 Command and address signal setup -A10B 25H 0 0 1 0 0 1 0 1 2.5 ns
time
33 Command and address signal hold -A10B 10H 0 0 0 1 0 0 0 0 1 ns
time
34 Data signal input setup time
35 Data signal input hold time
-A10B 25H 0 0 1 0 0 1 0 1 2.5 ns
-A10B 10H 0 0 0 1 0 0 0 0 1 ns
36-61
00H 0 0 0 0 0 0 0 0
62 SPD revision
-A10B 12H 0 0 0 1 0 0 1 0 1.2
63 Checksum for bytes 0 – 62
B5H 1 0 1 1 0 1 0 1
64-71 Manufacture’s JEDEC ID code
72 Manufacturing location
73-90 Manufacture’s P/N
91-92 Revision code
93-94 Manufacturing date
95-98 Assembly serial number
99-125 Mfg specific
126 Intel specification frequency
-A10B 66H 0 1 1 0 0 1 1 0 66 MHz
127 Intel specification /CAS latency
support
-A10B 06H 0
0
00
0110
Timing Chart
Refer to the SYNCHRONOUS DRAM MODULE TIMING CHART Information (M13348E).
Data Sheet M12263EJAV0DS00
11
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet MC-458CB64PSB.PDF ] | |
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