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Número de pieza | MC-4R128FKE8S | |
Descripción | Direct Rambus DRAM SO-RIMM Module 128M-BYTE (64M-WORD x 18-BIT) | |
Fabricantes | Elpida Memory | |
Logotipo | ||
Hay una vista previa y un enlace de descarga de MC-4R128FKE8S (archivo pdf) en la parte inferior de esta página. Total 14 Páginas | ||
No Preview Available ! DATA SHEET
MOS INTEGRATED CIRCUIT
MC-4R128FKE8S
Direct Rambus DRAM SO-RIMMTM Module
128M-BYTE (64M-WORD x 18-BIT)
Description
The Direct Rambus SO-RIMM module is a general-purpose high-performance memory module subsystem suitable
for use in a broad range of applications including computer memory, mobile personal computers, networking
systems, and other applications where high bandwidth and low latency are required.
MC-4R128FKE8S modules consists of four 288M Direct Rambus DRAM (Direct RDRAM) devices (µPD488588).
These are extremely high-speed CMOS DRAMs organized as 16M words by 18 bits. The use of Rambus Signaling
Level (RSL) technology permits 800MHz transfer rates while using conventional system and board design
technologies.
Direct RDRAM devices are capable of sustained data transfers at 1.25 ns per two bytes (10 ns per 16 bytes).
The architecture of the Direct RDRAM enables the highest sustained bandwidth for multiple, simultaneous,
randomly addressed memory transactions. The separate control and data buses with independent row and column
control yield high bus efficiency. The Direct RDRAM's multi-bank architecture supports up to four simultaneous
transactions per device.
Features
• 160 edge connector pads with 0.65mm pad spacing
• 128 MB Direct RDRAM storage
• Each RDRAM has 32 banks, for 128 banks total on module
• Gold plated contacts
• RDRAMs use Chip Scale Package (CSP)
• Serial Presence Detect support
• Operates from a 2.5 V supply
• Powerdown self refresh modes
• Separate Row and Column buses for higher efficiency
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local Elpida Memory, Inc. for
availability and additional information.
Document No. E0139N30 (Ver. 3.0)
Date Published June 2002 (K) Japan
URL: http://www.elpida.com
Elpida Memory,Inc. 2001-2002
Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd.
1 page MC-4R128FKE8S
Module Connector Pad Description
(1/2)
Signal
GND
LCFM
I/O
–
I
LCFMN
I
LCMD
I
LCOL4..LCOL0
I
LCTM
I
LCTMN
I
LDQA8..LDQA0 I/O
LDQB8..LDQB0 I/O
LROW2..LROW0
LSCK
I
I
NC –
RCFM
I
RCFMN
I
RCMD
I
RCOL4..RCOL0
I
RCTM
I
RCTMN
I
RDQA8..RDQA0 I/O
RDQB8..RDQB0 I/O
RROW2..RROW0 I
Type
–
RSL
RSL
VCMOS
RSL
RSL
RSL
RSL
RSL
RSL
VCMOS
–
RSL
RSL
VCMOS
RSL
RSL
RSL
RSL
RSL
RSL
Description
Ground reference for RDRAM core and interface.
Clock from master. Interface clock used for receiving RSL signals from the
Channel. Positive polarity.
Clock from master. Interface clock used for receiving RSL signals from the
Channel. Negative polarity.
Serial Command used to read from and write to the control registers. Also used
for power management.
Column bus. 5-bit bus containing control and address information for column
accesses.
Clock to master. Interface clock used for transmitting RSL signals to the
Channel. Positive polarity.
Clock to master. Interface clock used for transmitting RSL signals to the
Channel. Negative polarity.
Data bus A. A 9-bit bus carrying a byte of read or write data between the Channel
and the RDRAM. LDQA8 is non-functional on modules with x16 RDRAM devices.
Data bus B. A 9-bit bus carrying a byte of read or write data between the Channel
and the RDRAM. LDQB8 is non-functional on modules with x16 RDRAM devices.
Row bus. 3-bit bus containing control and address information for row accesses.
Serial clock input. Clock source used to read from and write to the RDRAM
control registers.
These pads are not connected. These 8 connector pads are reserved for future
use.
Clock from master. Interface clock used for receiving RSL signals from the
Channel. Positive polarity.
Clock from master. Interface clock used for receiving RSL signals from the
Channel. Negative polarity.
Serial Command Input used to read from and write to the control registers. Also
used for power management.
Column bus. 5-bit bus containing control and address information for column
accesses.
Clock to master. Interface clock used for transmitting RSL signals to the
Channel. Positive polarity.
Clock to master. Interface clock used for transmitting RSL signals to the
Channel. Negative polarity.
Data bus A. A 9-bit bus carrying a byte of read or write data between the Channel
and the RDRAM. RDQA8 is non-functional on modules with x16 RDRAM devices.
Data bus B. A 9-bit bus carrying a byte of read or write data between the Channel
and the RDRAM. RDQB8 is non-functional on modules with x16 RDRAM devices.
Row bus. 3-bit bus containing control and address information for row accesses.
Data Sheet E0139N30 (Ver. 3.0)
5
5 Page MC-4R128FKE8S
Package Drawings
160 EDGE CONNECTOR PADS RIMM (SOCKET TYPE) (1/2)
EEPROM
A (AREA B)
R 288M Direct RDRAM x 4
M1 (AREA B)
PS
ON M
G
LA
D EF
B
C
A1 (AREA A)
KH
IJ
Q
M2 (AREA A)
detail of A part
C1 W
R0.75
Y B1
XZ
Data Sheet E0139N30 (Ver. 3.0)
T
ITEM
A
A1
B
B1
C
C1
D
E
F
G
H
I
J
K
L
M
M1
M2
N
O
P
Q
R
S
T
W
X
Y
Z
MILLIMETERS
67.60 TYP.
67.60 ± 0.15
30.00
0.75 ± 0.10
4.00
4.00 ± 0.10
25.35
13.60
25.35
1.65
21.00
17.00
21.00
4.30
0.65 TYP.
31.25 ± 0.15
8.75
22.50
29.25
20.00
5.00 ± 0.10
R1.00
1.00 ± 0.10
φ2.00
1.0 ± 0.10
0.43 ± 0.03
2.55 MIN.
0.25 MAX.
1.50 ± 0.10
ECA-TS2-0034-02
11
11 Page |
Páginas | Total 14 Páginas | |
PDF Descargar | [ Datasheet MC-4R128FKE8S.PDF ] |
Número de pieza | Descripción | Fabricantes |
MC-4R128FKE8D | Direct Rambus DRAM RIMM Module 128M-BYTE (64M-WORD x 18-BIT) | Elpida Memory |
MC-4R128FKE8S | Direct Rambus DRAM SO-RIMM Module 128M-BYTE (64M-WORD x 18-BIT) | Elpida Memory |
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