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PDF MH16S64APFC-8 Data sheet ( Hoja de datos )
| Número de pieza | MH16S64APFC-8 | |
| Descripción | 1 /073 /741 /824-BIT (16 /777 /216 - WORD BY 64-BIT)SynchronousDRAM | |
| Fabricantes | Mitsubishi | |
| Logotipo |  |
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Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH16S64APFC -7,-7L,-8,-8L
1,073,741,824-BIT (16,777,216 - WORD BY 64-BIT)SynchronousDRAM
DESCRIPTION
The MH16S64APFC is 16777216 - word by 64-bit
Synchronous DRAM module. This consists of eight
industry standard 8Mx16 Synchronous DRAMs in
TSOP and one industory standard EEPROM in
TSSOP.
The mounting of TSOP on a card edge Dual
Inline package provides any application where
high densities and large quantities of memory are
required.
This is a socket type - memory modules, suitable
for easy interchange or addition of modules.
FEATURES
Utilizes industry standard 8M x 16 Sy nchronous DRAMs
TSOP and industry standard EEPROM in TSSOP
144-pin (72-pin dual in-line package)
single 3.3V±0.3V power supply
Clock frequency 100MHz(max.)
Fully synchronous operation referenced to clock rising
edge
4 bank operation controlled by BA0,1(Bank Address)
/CAS latency- 2/3(programmable)
Burst length- 1/2/4/8/Full Page(programmable)
-7,-7L
-8,-8L
Frequency
CLK Access Time
(Component SDRAM)
100MHz
6.0ns(CL=2)
100MHz
6.0ns(CL=3)
Burst type- sequential / interleave(programmable)
Column access - random
Auto precharge / All bank precharge controlled by A10
Auto refresh and Self refresh
4096 refresh cycle /64ms
PC100 compliant
LVTTL Interface
APPLICATION
main memory or graphic memory in computer systems
PCB Outline
(Front)
(Back)
1
2
MIT-DS-0375-0.1
MITSUBISHI
ELECTRIC
( 1 / 55 )
143
144
16.Mar.2000
1 page  
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH16S64APFC -7,-7L,-8,-8L
1,073,741,824-BIT (16,777,216 - WORD BY 64-BIT)SynchronousDRAM
Serial Presence Detect Table II
31
32
33
34
35
36-61
62
63
Density of each bank on module
Command and Address signal input setup time
Command and Address signal input hold time
Data signal input setup time
Data signal input hold time
Superset Information (may be used in future)
SPD Revision
Checksum for bytes 0-62
64-71
72
Manufactures Jedec ID code per JEP-108E
Manufacturing location
73-90
Manufactures Part Number
91-92
93-94
95-98
99-125
126
127
128+
Revision Code
Manufacturing date
Assembly Serial Number
Manufacture Specific Data
Intetl specification frequency
Intel specification CAS# Latency support
Unused storage locations
-7,7L-8,8L
-7,7L
-8,8L
64MByte
2ns
1ns
2ns
1ns
option
rev 1.2A
Check sum for -7,7L
Check sum for -8,-8L
MITSUBISHI
Miyoshi,Japan
Tajima,Japan
NC,USA
Germany
MH16S64APFC-7
MH16S64APFC-7L
MH16S64APFC-8
MH16S64APFC-8L
PCB revision
year/week code
serial number
option
100MHz
open
10
20
10
20
10
00
12
4E
0E
1CFFFFFFFFFFFFFF
01
02
03
04
4D483136533634415046432D372020202020
4D483136533634415046432D374C20202020
4D483136533634415046432D382020202020
4D483136533634415046432D384C20202020
rrrr
yyww
ssssssss
00
64
8F
8D
00
MIT-DS-0375-0.1
MITSUBISHI
ELECTRIC
( 5 / 55 )
16.Mar.2000
5 Page 
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH16S64APFC -7,-7L,-8,-8L
1,073,741,824-BIT (16,777,216 - WORD BY 64-BIT)SynchronousDRAM
FUNCTION TRUTH TABLE(continued)
Current State
PRE -
CHARGING
ROW
ACT IVATING
WRITE RE-
COVERING
/S /RAS /CAS /WE Address
Command
Action
H X X XX
DESEL NOP(Idle after tRP)
L H H HX
NOP
NOP(Idle after tRP)
L H H L BA
TBST
ILLEGAL*2
L H L X BA,CA,A10 READ/WRITE ILLEGAL*2
L L H H BA,RA
ACT ILLEGAL*2
L L H L BA,A10
PRE/PREA NOP*4(Idle after tRP)
L L L HX
REFA
ILLEGAL
Op-Code,
LLLL
Mode-Add
MRS
ILLEGAL
H X X XX
DESEL NOP(Row Active after tRCD
L H H HX
NOP
NOP(Row Active after tRCD
L H H L BA
TBST
ILLEGAL*2
L H L X BA,CA,A10 READ/WRITE ILLEGAL*2
L L H H BA,RA
ACT ILLEGAL*2
L L H L BA,A10
PRE/PREA ILLEGAL*2
L L L HX
REFA
ILLEGAL
Op-Code,
LLLL
Mode-Add
MRS
ILLEGAL
H X X XX
DESEL NOP
L H H HX
NOP
NOP
L H H L BA
TBST
ILLEGAL*2
L H L X BA,CA,A10 READ/WRITE ILLEGAL*2
L L H H BA,RA
ACT ILLEGAL*2
L L H L BA,A10
PRE/PREA ILLEGAL*2
L L L HX
REFA
ILLEGAL
Op-Code,
LLLL
Mode-Add
MRS
ILLEGAL
MIT-DS-0375-0.1
MITSUBISHI
ELECTRIC
( 11 / 55 )
16.Mar.2000
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet MH16S64APFC-8.PDF ] | |
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