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PDF MH16S72APHB-6 Data sheet ( Hoja de datos )
| Número de pieza | MH16S72APHB-6 | |
| Descripción | 1 /207 /959 /552-BIT (16 /777 /216 - WORD BY 72-BIT)Synchronous DRAM | |
| Fabricantes | Mitsubishi | |
| Logotipo |  |
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Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH16S72APHB -6,-7,-8
1,207,959,552-BIT (16,777,216 - WORD BY 72-BIT)Synchronous DRAM
DESCRIPTION
The MH16S72APHB is 16777216 - word by 72-bit
Synchronous DRAM module. This consists of nine
industry standard 16Mx8 Synchronous DRAMs in
TSOP and one industory standard EEPROM in
TSSOP.
The mounting of TSOP on a card edge Dual
Inline package provides any application where
high densities and large quantities of memory are
required.
This is a socket type - memory modules, suitable
for easy interchange or addition of modules.
FEATURES
Frequency
CLK Access Time
(Component SDRAM)
-6 133MHz 5.4ns(CL=3)
-7 100MHz 6.0ns(CL=2)
-8 100MHz 6.0ns(CL=3)
Utilizes industry standard 16M x 8 Sy nchronous DRAMs
TSOP and industry standard EEPROM in TSSOP
168-pin (84-pin dual in-line package)
single 3.3V±0.3V power supply
Max. Clock frequency -6:133MHz,-7,8:100MHz
Fully synchronous operation referenced to clock
rising edge
4 bank operation controlled by BA0,1(Bank Address)
/CAS latency- 2/3(programmable)
Burst length- 1/2/4/8/Full Page(programmable)
Burst type- sequential / interleave(programmable)
Column access - random
Auto precharge / All bank precharge controlled by A10
Auto refresh and Self refresh
4096 refresh cycle /64ms
LVTTL Interface
Discrete IC and module design conform to
PC100/PC133 specification.
85pin 1pin
94pin
95pin
10pin
11pin
124pin 40pin
125pin 41pin
168pin 84pin
APPLICATION
PC main memory
MIT-DS-0378-0.1
MITSUBISHI
ELECTRIC
( 1 / 55 )
17.Mar.2000
1 page  
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH16S72APHB -6,-7,-8
1,207,959,552-BIT (16,777,216 - WORD BY 72-BIT)Synchronous DRAM
Serial Presence Detect Table II
31 Density of each bank on module
32 Command and Address signal input setup time
33 Command and Address signal input hold time
34
35
36-61
62
63
Data signal input setup time
Data signal input hold time
Superset Information (may be used in future)
SPD Revision
Checksum for bytes 0-62
-6
-7,-8
-6
-7,-8
-6
-7,-8
-6
-7,-8
64-71
72
Manufactures Jedec ID code per JEP-108E
Manufacturing location
73-90
Manufactures Part Number
91-92
93-94
95-98
99-125
126
127
128+
Revision Code
Manufacturing date
Assembly Serial Number
Manufacture Specific Data
Intetl specification frequency
Intel specification CAS# Latency support
Unused storage locations
-6,-7
-8
128MByte
1.5ns
2ns
0.8ns
1ns
1.5ns
2ns
0.8ns
1ns
option
rev 1.2B
Check sum for -6
Check sum for -7
Check sum for -8
MITSUBISHI
Miyoshi,Japan
Tajima,Japan
NC,USA
Germany
MH16S72APHB-6
MH16S72APHB-7
MH16S72APHB-8
PCB revision
year/week code
serial number
option
100MHz
CL=2/3,AP,CK0,2
CL=3,AP,CK0,2
open
20
15
20
08
10
15
20
08
10
00
12
C7
28
68
1CFFFFFFFFFFFFFF
01
02
03
04
4D483136533732415048422D362020202020
4D483136533732415048422D372020202020
4D483136533732415048422D382020202020
rrrr
yyww
ssssssss
00
64
AF
AD
00
MIT-DS-0378-0.1
MITSUBISHI
ELECTRIC
( 5 / 55 )
17.Mar.2000
5 Page 
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH16S72APHB -6,-7,-8
1,207,959,552-BIT (16,777,216 - WORD BY 72-BIT)Synchronous DRAM
FUNCTION TRUTH TABLE(continued)
Current State
PRE -
CHARGING
ROW
ACT IVATING
WRITE RE-
COVERING
/S /RAS /CAS /WE Address
Command
Action
H X X XX
DESEL NOP(Idle after tRP)
L H H HX
NOP
NOP(Idle after tRP)
L H H L BA
TBST
ILLEGAL*2
L H L X BA,CA,A10 READ/WRITE ILLEGAL*2
L L H H BA,RA
ACT ILLEGAL*2
L L H L BA,A10
PRE/PREA NOP*4(Idle after tRP)
L L L HX
REFA
ILLEGAL
Op-Code,
LLLL
Mode-Add
MRS
ILLEGAL
H X X XX
DESEL NOP(Row Active after tRCD
L H H HX
NOP
NOP(Row Active after tRCD
L H H L BA
TBST
ILLEGAL*2
L H L X BA,CA,A10 READ/WRITE ILLEGAL*2
L L H H BA,RA
ACT ILLEGAL*2
L L H L BA,A10
PRE/PREA ILLEGAL*2
L L L HX
REFA
ILLEGAL
Op-Code,
LLLL
Mode-Add
MRS
ILLEGAL
H X X XX
DESEL NOP
L H H HX
NOP
NOP
L H H L BA
TBST
ILLEGAL*2
L H L X BA,CA,A10 READ/WRITE ILLEGAL*2
L L H H BA,RA
ACT ILLEGAL*2
L L H L BA,A10
PRE/PREA ILLEGAL*2
L L L HX
REFA
ILLEGAL
Op-Code,
LLLL
Mode-Add
MRS
ILLEGAL
MIT-DS-0378-0.1
MITSUBISHI
ELECTRIC
( 11 / 55 )
17.Mar.2000
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet MH16S72APHB-6.PDF ] | |
Hoja de datos destacado
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| MH16S72APHB-7 | 1 /207 /959 /552-BIT (16 /777 /216 - WORD BY 72-BIT)Synchronous DRAM | Mitsubishi |
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