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74LVQ138 fiches techniques PDF

Fairchild Semiconductor - Low Voltage 1-of-8 Decoder/Demultiplexer

Numéro de référence 74LVQ138
Description Low Voltage 1-of-8 Decoder/Demultiplexer
Fabricant Fairchild Semiconductor 
Logo Fairchild Semiconductor 





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74LVQ138 fiche technique
May 1998
74LVQ138
Low Voltage 1-of-8 Decoder/Demultiplexer
General Description
The LVQ138 is a high-speed 1-of-8 decoder/demultiplexer.
This device is ideally suited for high-speed bipolar memory
chip select address decoding. The multiple input enables al-
low parallel expansion to a 1-of-24 decoder using just three
LVQ138 devices or a 1-of-32 decoder using four LVQ138 de-
vices and one inverter.
Features
n Ideal for low power/low noise 3.3V applications
n Guaranteed simultaneous switching noise level and
dynamic threshold performance
n Improved latch-up immunity
n Guaranteed incident wave switching into 75
n 4 kV minimum ESD immunity
n Demultiplexing capability
n Multiple input enable for each expansion
n Active LOW mutually exclusive outputs
Ordering Code:
Order Number Package Number
Package Description
74LVQ138SC
M16A
16-Lead (0.150" Wide) Small Outline Integrated Circuit, SOIC JEDEC
74LVQ138SJ
M16D
16-Lead Molded Small Outline Package, SOIC EIAJ
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbols
Connection Diagram
Pin Assignment
for SOIC JEDEC and EIAJ
DS011350-1
IEEE/IEC
DS011350-4
DS011350-2
Pin Descriptions
Pin Names
A0– A2
E1– E2
E3
O0– O7
Description
Address Inputs
Enable Inputs
Enable Input
Outputs
© 1998 Fairchild Semiconductor Corporation DS011350
www.fairchildsemi.com

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