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PDF 74LVQ74 Data sheet ( Hoja de datos )
| Número de pieza | 74LVQ74 | |
| Descripción | DUAL D-TYPE FLIP FLOP WITH PRESET AND CLEAR | |
| Fabricantes | STMicroelectronics | |
| Logotipo |  |
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® 74LVQ74
DUAL D-TYPE FLIP FLOP WITH PRESET AND CLEAR
s HIGH SPEED:
fMAX = 250 MHz (TYP.) at VCC = 3.3V
s COMPATIBLE WITH TTL OUTPUTS
s LOW POWER DISSIPATION:
ICC = 2 µA (MAX.) at TA = 25 oC
s LOW NOISE:
VOLP = 0.2 V (TYP.) at VCC = 3.3V
s 75Ω TRANSMISSION LINE DRIVING
CAPABILITY
s SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 12 mA (MIN)
s PCI BUS LEVELS GUARANTEED AT 24mA
s BALANCED PROPAGATION DELAYS:
tPLH ≅ tPHL
s OPERATING VOLTAGE RANGE:
VCC (OPR) = 2V to 3.6V (1.2V Data Retention)
s PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 74
s IMPROVED LATCH-UP IMMUNITY
DESCRIPTION
The LVQ74 is a low voltage CMOS DUAL
D-TYPE FLIP FLOP WITH PRESET AND CLEAR
NON INVERTING fabricated with sub-micron
silicon gate and double-layer metal wiring C2MOS
technology. It is ideal for low power and low noise
M
(Micro Package)
T
(TSSOP Package)
ORDER CODES :
74LVQ74M
74LVQ74T
3.3V applications.
A signal on the D INPUT is transferred to the Q
OUTPUT during the positive going transition of
the clock pulse.
CLEAR and PRESET are independent of the
clock and accomplished by a low setting on the
appropriate input.
It has better speed performance at 3.3V than 5V
LSTTL family combined with the true CMOS low
power consumption.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
PIN CONNECTION AND IEC LOGIC SYMBOLS
February 1999
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1 page  
74LVQ74
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, RL = 500 Ω, Input tr = tf =3 ns)
Symb ol
Parameter
T est Con ditio n
VCC
(V)
Valu e
TA = 25 oC
-40 to 85 oC
Min. T yp. Max. Min. Max.
Unit
tPLH Propagation Delay Time
tPHL CK to Q
2.7
3.3(*)
8.0 19.0
6.5 13.0
21.0
14.0
ns
tPLH Propagation Delay Time
tPHL PR or CLR to Q
2.7
3.3(*)
7.0 16.0
6.0 12.0
19.0
13.0
ns
tw Pulse Width CK, HIGH
or LOW
2.7
3.3(*)
1.5 7.0
1.5 5.0
10.0 ns
7.0
tw(L) Pulse Width PR or CLR,
LOW
2.7
3.3(*)
1.5 7.0
1.5 5.0
10.0 ns
7.0
ts Setup Time D to CK
HIGH or LOW
2.7
3.3(*)
-0.2 5.0
-0.2 4.0
6.0 ns
5.0
th Hold Time Q to CK
HIGH or LOW
2.7
3.3(*)
0.2 2.0
0.2 2.0
2.0 ns
2.0
tREM Recovery Time PR or
CLR to Q
2.7
3.3(*)
-1.0 1.0
-1.0 1.0
1.0
ns
1.0
fMAX Maximum Clock
Frequency
2.7
3.3(*)
60 200 40 MHz
100 250
100
tOSLZ Output to Output Skew
tOSHL Time (note 1, 2)
2.7
3.3(*)
0.5 1.0
0.5 1.0
1.5 ns
1.5
1) Skew is defined as the absolute value of the difference between the actual propagation delay for any twooutputs of the same device switching in the
same direction, either HIGH or LOW
2) Parameter guaranteed by design
CAPACITIVE CHARACTERISTICS
Symb ol
Parameter
Test Conditions
VCC
(V)
Valu e
TA = 25 oC
-40 to 85 oC
Min. T yp. Max. Min. Max.
Unit
CIN Input Capacitance
3.3
4 pF
CPD Power Dissipation
3.3 fIN = 10 MHz
Capacitance (note 1)
33
pF
1) CPD isdefined as the value of the IC’sinternal equivalent capacitance which is calculated fromthe operating current consumption without load. (Referto
Test Circuit).Average operting current can be obtained by the following equation. ICC(opr) = CPD • VCC • fIN + ICC/n(per circuit)
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5 Page 
74LVQ74
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is
granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are
subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products
are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a trademark of STMicroelectronics
© 1999 STMicroelectronics – Printed in Italy – All Rights Reserved
STMicroelectronics GROUP OF COMPANIES
Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Mexico - Morocco - The Netherlands -
Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A.
http://www.st.com
.
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| Páginas | Total 11 Páginas | |
| PDF Descargar | [ Datasheet 74LVQ74.PDF ] | |
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