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74VHC08T fiches techniques PDF

STMicroelectronics - QUAD 2-INPUT AND GATE

Numéro de référence 74VHC08T
Description QUAD 2-INPUT AND GATE
Fabricant STMicroelectronics 
Logo STMicroelectronics 





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74VHC08T fiche technique
74VHC08
QUAD 2-INPUT AND GATE
s HIGH SPEED: tPD = 4.3 ns (TYP.) at VCC = 5V
s LOW POWER DISSIPATION:
ICC = 2 µA (MAX.) at TA=25°C
s HIGH NOISE IMMUNITY:
VNIH = VNIL = 28% VCC (MIN.)
s POWER DOWN PROTECTION ON INPUTS
s SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 8mA (MIN)
s BALANCED PROPAGATION DELAYS:
tPLH tPHL
s OPERATING VOLTAGE RANGE:
VCC(OPR) = 2V to 5.5V
s PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 08
s IMPROVED LATCH-UP IMMUNITY
s LOW NOISE: VOLP = 0.8V (MAX.)
DESCRIPTION
The 74VHC08 is an advanced high-speed CMOS
QUAD 2-INPUT AND GATE fabricated with
sub-micron silicon gate and double-layer metal
wiring C2MOS technology.
The internal circuit is composed of 2 stages
including buffer output, which provides high noise
immunity and stable output.
SOP
TSSOP
Table 1: Order Codes
PACKAGE
SOP
TSSOP
T&R
74VHC08MTR
74VHC08TTR
Power down protection is provided on all inputs
and 0 to 7V can be accepted on inputs with no
regard to the supply voltage. This device can be
used to interface 5V to 3V.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
Figure 1: Pin Connection And IEC Logic Symbols
November 2004
Rev. 5
1/11

PagesPages 11
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