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Numéro de référence | 74VHC132 | ||
Description | QUAD 2-INPUT SCHMITT NAND GATE | ||
Fabricant | STMicroelectronics | ||
Logo | |||
1 Page
74VHC132
QUAD 2-INPUT SCHMITT NAND GATE
s HIGH SPEED: tPD = 3.9 ns (TYP.) at VCC = 5V
s LOW POWER DISSIPATION:
ICC = 2 µA (MAX.) at TA=25°C
s TYPICAL HYSTERESIS:
Vh = 1V at VCC = 4.5V
s POWER DOWN PROTECTION ON INPUTS
)s SYMMETRICAL OUTPUT IMPEDANCE:
t(s|IOH| = IOL = 8 mA (MIN)
cs BALANCED PROPAGATION DELAYS:
utPLH ≅ tPHL
ds OPERATING VOLTAGE RANGE:
roVCC(OPR) = 2V to 5.5V
Ps PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 132
tes IMPROVED LATCH-UP IMMUNITY
les LOW NOISE: VOLP = 0.8V (MAX.)
bsoDESCRIPTION
OThe 74VHC132 is an advanced high-speed
-CMOS QUAD 2-INPUT SCHMITT NAND GATE
)fabricated with sub-micron silicon gate and
t(sdouble-layer metal wiring C2MOS technology.
Power down protection is provided on all inputs
cand 0 to 7V can be accepted on inputs with no
duregard to the supply voltage. This device can be
roused to interface 5V to 3V.
SOP
TSSOP
Table 1: Order Codes
PACKAGE
SOP
TSSOP
T&R
74VHC132MTR
74VHC132TTR
Pin configuration and function are the same as
those of the 74VHC00 but the 74VHC132 has
hysteresis.
This together with its schmitt trigger function
allows it to be used on line receivers with slow
rise/fall input signals.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
Obsolete PFigure 1: Pin Connection And IEC Logic Symbols
November 2004
Rev. 4
1/11
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Pages | Pages 11 | ||
Télécharger | [ 74VHC132 ] |
No | Description détaillée | Fabricant |
74VHC132 | QUAD 2-INPUT SCHMITT NAND GATE | STMicroelectronics |
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74VHC132 | Quad 2-Input NAND Schmitt Trigger | National Semiconductor |
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