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PDF 74VHCT132A Data sheet ( Hoja de datos )

Número de pieza 74VHCT132A
Descripción QUAD 2-INPUT SCHMITT NAND GATE
Fabricantes STMicroelectronics 
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No Preview Available ! 74VHCT132A Hoja de datos, Descripción, Manual

® 74VHCT132A
QUAD 2-INPUT SCHMITT NAND GATE
s HIGH SPEED: tPD = 6.5 ns (TYP.) at VCC = 5V
s LOW POWER DISSIPATION:
ICC = 2 µA (MAX.) at TA = 25 oC
s TYPICAL HYSTERESIS: 0.7V at VCC = 4.5V
s POWER DOWN PROTECTION ON INPUTS &
OUTPUTS
s SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 8 mA (MIN)
s BALANCED PROPAGATION DELAYS:
tPLH tPHL
s OPERATING VOLTAGE RANGE:
VCC (OPR) = 4.5V to 5.5V
s PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 132
s IMPROVED LATCH-UP IMMUNITY
s LOW NOISE: VOLP = 0.8V (Max.)
DESCRIPTION
The 74VHCT132A is an advanced high-speed
CMOS QUAD 2-INPUT SCHMITT NAND GATE
fabricated with sub-micron silicon gate and
double-layer metal wiring C2MOS technology.
Power down protection is provided on all inputs
and outputs and 0 to 7V can be accepted on
PRELIMINARY DATA
SOP
TSSOP
PACKAGE
SOP
TSSOP
ORDER CODES
T UB E
T&R
74VHCT132AM 74VHCT132AMTR
74VHCT132ATTR
inputs with no regard to the supply voltage. This
device can be used to interface 5V to 3V.
Pin configuration and function are the same as
those of the VHCT00A but the VHCT132A has
hysteresis.
This together with its schmitt trigger function
allows it to be used on line receivers with slow
rise/fall input signals.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
PIN CONNECTION AND IEC LOGIC SYMBOLS
February 2000
1/7

1 page




74VHCT132A pdf
DIM.
A
a1
a2
b
b1
C
c1
D
E
e
e3
F
G
L
M
S
MIN.
0.1
0.35
0.19
8.55
5.8
3.8
4.6
0.5
SO-14 MECHANICAL DATA
mm
TYP.
0.5
1.27
7.62
MAX.
1.75
0.2
1.65
0.46
0.25
MIN.
0.003
0.013
0.007
45 (typ.)
8.75 0.336
6.2 0.228
4.0 0.149
5.3 0.181
1.27 0.019
0.68
8 (max.)
74VHCT132A
inch
TYP.
0.019
0.050
0.300
MAX.
0.068
0.007
0.064
0.018
0.010
0.344
0.244
0.157
0.208
0.050
0.026
P013G
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