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PDF M30220 Data sheet ( Hoja de datos )

Número de pieza M30220
Descripción SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Fabricantes Mitsubishi 
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Preliminary Specifications REV.E
Mitsubishi microcomputers
Specifications in this manual are tentative and subject to change.
M30220 Group
Description
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Description
The M30220 group of single-chip microcomputers are built using the high-performance silicon gate CMOS
process using a M16C/60 Series CPU core. The M30220 group has LCD controller/driver. M30220 group is
packaged in a 144-pin plastic molded QFP. These single-chip microcomputers operate using sophisticated
instructions featuring a high level of instruction efficiency. With 1M bytes of address space, they are ca-
pable of executing instructions at high speed.
Features
• Basic machine instructions .................. Compatible with the M16C/60 series
• Memory capacity .................................. ROM 96 Kbytes
RAM 6 Kbytes
• Shortest instruction execution time ...... 100ns (f(XIN)=10MHz)
• Supply voltage ..................................... 4.0V to 5.5V (f(XIN)=10MHz)
2.7V to 5.5V (f(XIN)=7MHz with software one-wait)
• Interrupts .............................................. 25 internal and 8 external interrupt sources, 4 software, 7 levels
(including key input interrupt)
• Multifunction 16-bit timer ...................... Timer A (output) x 8, timer B (input) x 6
• Real time port outputs .......................... 8 bits X 4 lines
• Serial I/O .............................................. 3 channel for UART or clock synchronous
• DMAC .................................................. 2 channels (trigger: 24 sources)
• A-D converter ....................................... 10 bits X 8 channels
• D-A converter ....................................... 8 bits X 3 channels
• Watchdog timer .................................... 1 line
• Programmable I/O ............................... 104 lines (32 lines are shared with LCD outputs)
_______
• Input port .............................................. 1 line (P77, shared with NMI pin) Specifications written in this manual
• LCD drive control circuit ....................... 1/2, 1/3 bias
are believed to be accurate, but are
2, 3 and 4 time sharing
4 common outputs
48 segment outputs
not guaranteed to be entirely free of
error.
Specifications in this manual may
be changed for functional or
built-in set-up condencer circuit performance improvements. Please
• Key input interrupt ................................ 20 lines
make sure your manual is the latest
edition.
• Clock generating circuit ....................... 2 built-in clock generation circuits
(built-in feedback resistor, and external ceramic or quartz oscillator)
Applications
Camera, Home appliances, Portable equipment, Audio, office equipment, etc.
------Table of Contents------
Central Processing Unit (CPU) ....................... 9
Reset ............................................................. 12
Clock Generating Circuit ............................... 20
Protection ...................................................... 29
Interrupt ......................................................... 30
Watchdog Timer ............................................ 53
DMAC ........................................................... 55
Timer ............................................................. 65
Real time Port ............................................... 85
Serial I/O ....................................................... 87
LCD Drive Control Circuit ............................ 123
A-D Converter ............................................. 130
D-A Converter ............................................. 140
Programmable I/O Port ............................... 142
Electric Characteristics ............................... 155
Flash Memory Version ................................ 168
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M30220 pdf
Preliminary Specifications REV.E
Mitsubishi microcomputers
Specifications in this manual are tentative and subject to change.
M30220 Group
Description
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Mitsubishi plans to release the following products in the M30220 group:
(1) Support for mask ROM version, flash memory version
(2) ROM capacity
(3) Package
144P6Q-A : Plastic molded QFP (mask ROM and flash memory versions)
144PFB-A : Plastic molded QFP(mask ROM and flash memory versions)
Figure 1.1.3 shows the ROM expansion and figure 1.1.4 shows the Type No., memory size, and package.
RAM
(Byte)
10K
6K
October. 1999
Under development
M30220FCGP/RP
Under development
M30220MA-XXXGP/RP
Figure 1.1.3. ROM expansion
96K
128K
ROM
(Byte)
Type No. M30 22 0 M A
- XXX GP
Package type:
GP: Package144P6Q-A
RP: 144PFB-A
ROM No.
Omitted for flash memory version
Shows characteristic, use
None: General
ROM capacity:
A : 96K bytes C : 128K bytes
Memory type:
M : Mask ROM version
F : Flash memory version
Shows RAM capacity, pin count, etc.
(The value itself has no specific meaning)
M16C/22 Group(built-in LCD)
M16C Family
Figure 1.1.4. Type No., memory size, and package
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M30220 arduino
Preliminary Specifications REV.E
Mitsubishi microcomputers
Specifications in this manual are tentative and subject to change.
M30220 Group
CPU
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
• Bit 7: Stack pointer select flag (U flag)
Interrupt stack pointer (ISP) is selected when this flag is “0” ; user stack pointer (USP) is selected
when this flag is “1”.
This flag is cleared to “0” when a hardware interrupt is acknowledged or an INT instruction of software
interrupt Nos. 0 to 31 is executed.
• Bits 8 to 11: Reserved area
• Bits 12 to 14: Processor interrupt priority level (IPL)
Processor interrupt priority level (IPL) is configured with three bits, for specification of up to eight
processor interrupt priority levels from level 0 to level 7.
If a requested interrupt has priority greater than the processor interrupt priority level (IPL), the interrupt
is enabled.
• Bit 15: Reserved area
The C, Z, S, and O flags are changed when instructions are executed. See the software manual for
details.
b15
IPL
b0
U I O B S Z D C Flag register (FLG)
Carry flag
Debug flag
Zero flag
Sign flag
Register bank select flag
Overflow flag
Interrupt enable flag
Stack pointer select flag
Reserved area
Processor interrupt priority level
Reserved area
Figure 1.5.2. Flag register (FLG)
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