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PDF M7020R Data sheet ( Hoja de datos )
| Número de pieza | M7020R | |
| Descripción | 32K x 68-bit Entry NETWORK SEARCH ENGINE | |
| Fabricantes | ST Microelectronics | |
| Logotipo |  |
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M7020R
32K x 68-bit Entry NETWORK SEARCH ENGINE
PRELIMINARY DATA
FEATURES SUMMARY
s 32K DATA ENTRIES IN 68-BIT MODE
s TABLE MAY BE PARTITIONED INTO UP TO
FOUR (4) QUADRANTS
(Data entry width in each octant is configurable
as 34, 68, 136, or 272 bits.)
s UP TO 83 MILLION SUSTAINED SEARCHES
PER SECOND IN 68-BIT and 136-BIT
CONFIGURATIONS
s UP TO 41.5 MILLION SEARCHES PER
SECOND IN 34-BIT and 272-BIT
CONFIGURATIONS
s SEARCHES ANY SUB-FIELD IN A SINGLE
CYCLE
s OFFERS BIT-BY-BIT and GLOBAL MASKING
s SYNCHRONOUS, PIPELINED OPERATION
s UP TO 31 SEARCH ENGINES CASCADABLE
WITHOUT PERFORMANCE DEGRADATION
s WHEN CASCADED, THE DATABASE
ENTRIES CAN SCALE FROM 248K TO 1984K
DEPENDING ON THE WIDTH OF THE ENTRY
s GLUELESS INTERFACE TO INDUSTRY-
STANDARD SRAMS
s SIMPLE HARDWARE INSTRUCTION
INTERFACE
s IEEE 1149.1 TEST ACCESS PORT
s OPERATING SUPPLY VOLTAGES INCLUDE:
VDD (Operating Supply Voltage) = 1.8V
VDDQ (Operating Supply Voltage for I/O) = 2.5
or 3.3V
s 272 PBGA, 27mm x 27mm
Figure 1. 272-ball PBGA Package
272-ball PBGA
27mm x 27mm
December 2001
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
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1 page  
M7020R
136-bit Search on Tables Configured as x136 Using Up to Eight M7020R Devices . . . . . . . . 66
Hit/Miss Assumption (Table 35.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Hardware Diagram for a Table with Eight Devices (Figure 44.) . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
x136 Table with Eight Devices (Figure 45.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Timing Diagrams for x136 Using Up to Eight M7020R Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
136-bit SEARCH for Device Number 0 (Figure 46.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
136-bit SEARCH for Device Number 1 (Figure 47.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
136-bit SEARCH for Device Number 7 (Last Device) (Figure 48.) . . . . . . . . . . . . . . . . . . . . . . 71
Latency of SEARCH from Instruction to SRAM Access Cycle, 136-bit, Up to 8 Devices . . . . . . . . 72
Shift of SSF and SSV from SADR (Table 37.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
136-bit Search on Tables Configured as x136 Using Up to 31 M7020R Devices. . . . . . . . . . . 72
Hit/Miss Assumption (Table 38.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Hardware Diagram for a Table with 31 Devices (Figure 49.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Hardware Diagram for a Block of Up to Eight Devices (Figure 50.) . . . . . . . . . . . . . . . . . . . . . . . . 75
x136 Table with 31 Devices (Figure 51.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Timing Diagrams for x136 Using Up to 31 M7020R Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Each Device in Block Number 0 (Miss on Each Device) (Figure 52.) . . . . . . . . . . . . . . . . . . . . 77
Each Device Above the Winning Device in Block Number 1 (Figure 53.) . . . . . . . . . . . . . . . . . 78
Globally Winning Device in Block Number 1 (Figure 54.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Devices Below the Winning Device in Block Number 1 (Figure 55.). . . . . . . . . . . . . . . . . . . . . 80
Devices Above the Winning Device in Block Number 2 (Figure 56.) . . . . . . . . . . . . . . . . . . . . 81
Globally Winning Device in Block Number 2 (Figure 57.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Devices Below the Winning Device in Block Number 2 (Figure 58.). . . . . . . . . . . . . . . . . . . . . 83
Devices Above the Winning Device in Block Number 3 (Figure 59.) . . . . . . . . . . . . . . . . . . . . 84
Globally Winning Device in Block Number 3 (Figure 60.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Devices Below the Winning Device in Block Number 3 (not Device 30 - Last Device) . . . . . . . 86
Device 6 in Block Number 3 (Device 30 in Depth-Cascaded Table) (Figure 62.) . . . . . . . . . . . 87
Latency of SEARCH from Instruction to SRAM Access Cycle, 136-bit, Up to 31 Devices . . . . . . . 88
Shift of SSF and SSV from SADR (Table 40.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
272-bit SEARCH on Tables Configured as x272 Using a Single M7020R Device . . . . . . . . . . 88
Hardware Diagram for a Table with One Device (Figure 63.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Timing Diagram for a 272-bit SEARCH for One Device (Figure 64.). . . . . . . . . . . . . . . . . . . . . . . . 90
x272 Table with One Device (Figure 65.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Latency of SEARCH from Cycles C and D to SRAM Access Cycle, 272-bit, 1 Device . . . . . . . . . . 91
Shift of SSF and SSV from SADR (Table 42.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
272-bit SEARCH on Tables x272-configured Using Up to Eight M7020R Devices . . . . . . . . . 92
Hit/Miss Assumption (Table 43.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Hardware Diagram for a Table with Eight Devices (Figure 66.) . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
x272 Table with Eight Devices (Figure 67.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Timing Diagrams for x272-configured Using Up to Eight M7020R Devices . . . . . . . . . . . . . . . . . . 96
272-bit SEARCH for Device Number 0 (Figure 68.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
272-bit SEARCH for Device Number 1 (Figure 69.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
272-bit SEARCH for Device Number 7 (Last Device) (Figure 70.) . . . . . . . . . . . . . . . . . . . . . . 98
Latency of SEARCH from Cycles C and D to SRAM Access Cycle, 272-bit, Up to 8 Devices . . . . 99
Shift of SSF and SSV from SADR (Table 45.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
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5 Page 
Figure 4. M7020R Block Diagram
PHS_L
CLK2X
RST_L
DQ [67:0]
Comparand Registers[15:0]
Global Mask Registers [7:0]
Information and Command Register
Burst Read Register
Burst Write Register
Next Free Address Register
Search Successful Index Registers [7:0]
(All registers are 68-bit-wide)
TAP
Controller
M7020R
TAP
CMD [8:0]
CMDV
ACK
EOT
Command
Decode
and PIO Access
ID [4:0]
FULL [6:0]
Full Logic
Cmd Compare/PIO Data
Configurable as
64K x 34
32K x 68
16K x 136
8K x 272
Data Array
Configurable as
64K x 34
32K x 68
16K x 136
8K x 272
Mask Array
Pipeline
and
SRAM
Control
SADR [21:0]
OE_L
WE_L
CE_L
ALE_L
FULL
LHI [6:0]
BHI [2:0]
FULO [1:0]
Arbitration
Logic
LHO [1:0]
BHO [2:0]
SSF
SSV
AI04271
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11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet M7020R.PDF ] | |
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