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PDF M74HC165 Data sheet ( Hoja de datos )
| Número de pieza | M74HC165 | |
| Descripción | 8 BIT PISO SHIFT REGISTER | |
| Fabricantes | ST Microelectronics | |
| Logotipo |  |
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M74HC165
8 BIT PISO SHIFT REGISTER
s HIGH SPEED :
tPD = 15ns (TYP.) at VCC = 6V
s LOW POWER DISSIPATION:
ICC =4µA(MAX.) at TA=25°C
s HIGH NOISE IMMUNITY:
VNIH = VNIL = 28 % VCC (MIN.)
s SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 4mA (MIN)
s BALANCED PROPAGATION DELAYS:
tPLH ≅ tPHL
s WIDE OPERATING VOLTAGE RANGE:
VCC (OPR) = 2V to 6V
s PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 165
DESCRIPTION
The M74HC165 is an high speed CMOS 8 BIT
PISO SHIFT REGISTER fabricated with silicon
gate C2MOS technology.
This device contains eight clocked master slave
RS flip-flops connected as a shift register, with
auxiliary gating to provide over-riding
asynchronous parallel entry. Parallel data enters
when the shift/load input is low. The parallel data
can change while shift/load is low, provided that
the recommended set-up and hold times are
observed. For clocked operation, shift/load must
DIP
SOP
TSSOP
ORDER CODES
PACKAGE
TUBE
DIP
SOP
TSSOP
M74HC165B1R
M74HC165M1R
T&R
M74HC165RM13TR
M74HC165TTR
be high. The two clock input perform identically;
one can be used as a clock inhibit by applying a
high signal; to permit this operation clocking is
accomplished through a 2 input nor gate.
To avoid double clocking, however, the inhibit
signal should only go high while the clock is high.
Otherwise the rising inhibit signal will cause the
same response as rising clock edge.
All inputs are equipped with protection circuits
against static discharge and transient excess
voltage.
PIN CONNECTION AND IEC LOGIC SYMBOLS
July 2001
1/12
1 page  
M74HC165
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6ns)
Test Condition
Value
Symbol
Parameter
VCC
(V)
tTLH tTHL Output Transition
Time
tPLH tPHL Propagation Delay
Time
(CLOCK - QH, QH)
tPLH tPHL Propagation Delay
Time
(SHIFT/LOAD -
QH, QH)
tPLH tPHL Propagation Delay
Time
(H - QH, QH)
fMAX Maximum Clock
Frequency
tW(H)
tW(L)
tW(L)
ts
th
tREM
Minimum Pulse
Width
(CLOCK)
Minimum Pulse
Width
(SHIFT/LOAD)
Minimum Set-up
Time
(PI - SHIFT/LOAD)
(SI - CLOCK)
(SHIFT/LOAD - CK)
Minimum Hold
Time
(PI - SHIFT/LOAD)
(SI - CLOCK)
(SHIFT/LOAD - CK)
Minimum Removal
Time
(CLOCK - CK INH)
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
TA = 25°C
-40 to 85°C -55 to 125°C Unit
Min.
Typ.
30
8
7
55
18
15
65
21
18
Max.
75
15
13
150
30
26
165
33
28
Min.
Max.
95
19
16
190
38
33
205
41
35
Min.
250
Max.
110
22
19
225
45
38
50
43
ns
ns
ns
52 135 170 205
17 27 34 41 ns
14 23 29 35
7.4 15
6.0 4.8
37 60 30 24 MHz
44 71 35 28
24 75
95 110
6 15 19 22 ns
5 13 16 19
32 75
95 110
8 15 19 22 ns
7 13 16 19
24 75
95 110
6 15 19 22
ns
5 13 16 19
000
000
ns
000
20 75
5 15
4 13
95 110
19 22 ns
16 19
CAPACITIVE CHARACTERISTICS
Test Condition
Value
Symbol
Parameter
VCC
(V)
TA = 25°C
-40 to 85°C -55 to 125°C Unit
Min. Typ. Max. Min. Max. Min. Max.
CIN Input Capacitance 5.0
5 10 10 10 pF
CPD Power Dissipation
Capacitance (note 5.0
1)
55
pF
1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC
5/12
5 Page 
DIM.
A
A1
A2
b
c
D
E
E1
e
K
L
M74HC165
MIN.
0.05
0.8
0.19
0.09
4.9
6.2
4.3
0°
0.45
TSSOP16 MECHANICAL DATA
mm.
TYP
1
5
6.4
4.4
0.65 BSC
0.60
MAX.
1.2
0.15
1.05
0.30
0.20
5.1
6.6
4.48
8°
0.75
MIN.
inch
TYP.
0.002
0.031
0.007
0.004
0.193
0.244
0.169
0°
0.018
0.004
0.039
0.197
0.252
0.173
0.0256 BSC
0.024
MAX.
0.047
0.006
0.041
0.012
0.0089
0.201
0.260
0.176
8°
0.030
A A2
A1 b
e
D
PIN 1 IDENTIFICATION
1
KL
cE
E1
0080338D
11/12
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet M74HC165.PDF ] | |
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