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PDF M74HCT652 Data sheet ( Hoja de datos )
| Número de pieza | M74HCT652 | |
| Descripción | HCT651 OCTAL BUS TRANSCEIVER/REGISTER 3-STATE / INV. HCT652 OCTAL BUS TRANSCEIVER/REGISTER 3-STATE | |
| Fabricantes | ST Microelectronics | |
| Logotipo |  |
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M74HCT651
M74HCT652
HCT651 OCTAL BUS TRANSCEIVER/REGISTER (3-STATE, INV.)
HCT652 OCTAL BUS TRANSCEIVER/REGISTER (3-STATE)
. HIGH SPEED
fMAX = 60 MHz (TYP.) AT VCC = 5V
. COMPATIBLE WITH TTL OUTPUTS
VIH = 2 V (MIN.) AT VIL = 0.8V (MAX)
. LOW POWER DISSIPATION
ICC = 4 µA (MAX) AT TA = 25 oC
. OUTPUT DRIVE CAPABILITY
15 LSTTL LOADS
. SYMMETRICAL OUTPUT IMPEDANCE
IOH = IOL = 6 mA (mIN.)
. BALANCED PROPAGATION DELAYS
tPLH = tPHL
. PIN AND FUNCTION COMPATIBLE
WITH 54/74LS651/652
B1R
(Plastic Package)
M1R
(Micro Package)
ORDER CODES :
M74HCXXXM1R M74HCXXXB1R
DESCRIPTION
M74HCT651/652 are high speed CMOS OCTAL
BUS TRANSCEIVERS AND REGISTERS
(3-STATE), fabricated in silicon gate C2MOS
technology. They have the same high speed
performance of LSTTL combined with true CMOS
low power consumption. These devices consist of
bus transceiver circuits, D-type flip-flops, and control
circuitry arranged for multiplexed transmission of
data directly from the input bus or from the internal
storage registers. Enable GAB and GBA are
provided to control the transceiver functions. Select
AB and Select BA control pins are provided to select
whether real-time or stored data is transfered. A low
input level selects real-time data, and a high selects
stored data. Data on the A or B bus, or both, can be
stored in the internal D flip-flops by low-to-high
transitions at the appropriate clock pins (CLOCK AB
or CLOCK BA) regardless of the select or enable
control pins. When select AB and select BA are in the
real-time transfer mode, it is also possible to store
data without using the internal D-type flip-flops by
simultaneously enabling GAB and GBA. In this
configuration each output reinforces its input. Thus,
when all other data sources to the two sets of bus
lines are at high impedance, each set of bus lines will
remain at its last state. All inputs are equipped with
protection circuits against static discharge and
transient excess voltage.This integrated circuit has
input and output characteristics that are fully
compatible with 54/74 LSTTL logic families.
M54/74HCT devices are designed to directly
interface HSCMOS systems with TTL and NMOS
components. They are also plug in replacements for
LSTTL devices giving a reduction of power
consumption.
PIN CONNECTIONS (top view)
INPUT AND OUTPUT EQUIVALENT CIRCUIT
GAB, GAB, CAB,
SAB, SBA, CBA
A, B
October 1993
1/12
1 page  
M74HCT651/652
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
VCC Supply Voltage
-0.5 to +7
V
VI DC Input Voltage
-0.5 to VCC + 0.5
V
VO DC Output Voltage
-0.5 to VCC + 0.5
V
IIK DC Input Diode Current
± 20 mA
IOK DC Output Diode Current
± 20 mA
IO DC Output Source Sink Current Per Output Pin
± 35 mA
ICC or IGND DC VCC or Ground Current
± 70 mA
PD Power Dissipation
Tstg Storage Temperature
TL Lead Temperature (10 sec)
500 (*)
-65 to +150
300
mW
oC
oC
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these condition isnotimplied.
RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
VI
VO
Top
tr, tf
Parameter
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature:
Input Rise and Fall Time (VCC = 4.5 to 5.5V)
Value
4.5 to 5.5
0 to VCC
0 to VCC
-40 to +85
0 to 500
Unit
V
V
V
oC
ns
5/12
5 Page 
DIM.
A
a1
a2
b
b1
C
c1
D
E
e
e3
F
L
S
MIN.
0.10
0.35
0.23
15.20
10.00
7.40
0.50
SO24 MECHANICAL DATA
mm
TYP.
0.50
1.27
13.97
MAX.
2.65
0.20
2.45
0.49
0.32
MIN.
0.004
0.013
0.009
45° (typ.)
15.60
0.598
10.65
0.393
7.60 0.291
1.27 0.19
8° (max.)
L
M74HCT651/652
inch
TYP.
0.020
0.05
0.55
MAX.
0.104
0.007
0.096
0.019
0.012
0.614
0.420
0.299
0.050
c1
b
24
e3
D
e
13
s
E
1 12
11/12
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet M74HCT652.PDF ] | |
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