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PDF M80287 Data sheet ( Hoja de datos )
| Número de pieza | M80287 | |
| Descripción | 80-BIT HMOS* NUMERIC PROCESSOR EXTENSION | |
| Fabricantes | Intel | |
| Logotipo |  |
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M80287
80-BIT HMOS
NUMERIC PROCESSOR EXTENSION
Military
Y High Performance 80-Bit Internal
Architecture
Y Implements Proposed IEEE Floating
Point Standard 754
Y Expands M80286 10 Datatypes to
Include 32- 64- 80-Bit Floating Point
32- 64-Bit Integers and 18-Digit BCD
Operands
Y Object Code Compatible with M8087
Y Built-In Exception Handling
Y Operates in Both Real and Protected
Mode M80286 Systems
Y Available in a 40-Pin Cerdip Package
Y Protected Mode Operation Completely
Conforms to the M80286 Memory
Management and Protection
Mechanisms
Y Directly Extends M80286 10 Instruction
Set to Trigonometric Logarithmic
Exponential and Arithmetic Instructions
for All Datatypes
Y 8 x 80-Bit Individually Addressable
Numeric Register Stack
Y 6 8 10 MHz
Y Military Temperature Range
b55 C to a125 C (TC)
The Intel M80287 is a high performance numerics processor extension that extends the M80286 10 architec-
ture with floating point extended integer and BCD data types The M80286 20 computing system (M80286
and M80287) fully conforms to the proposed IEEE Floating Point Standard Using a numerics oriented archi-
tecture the M80287 adds over fifty mnemonics to the M80286 20 instruction set making the M80286 20 a
complete solution for high performance numeric processing The M80287 is implemented in N-channel deple-
tion load silicon gate technology (HMOS) and packaged in a 40-pin ceramic package The M80286 20 is
object code compatible with the M80286 20 and M8088 20 Intel’s HMOS III process provides superior
radiation tolerance for applications with stringent radiation requirements
HMOS is a patented process of Intel Corporation
Figure 1 M80287 Block Diagram
271029 – 1
NOTE
271029 – 2
N C pins must not be connected
Figure 2 M80287 Pin
Configuration
December 1990
Order Number 271029-005
1 page  
M80287
A C CHARACTERISTICS (Over Specified Operating Conditions)
TIMING REQUIREMENTS
A C timings are referenced to 0 8V and 2 0V points on signals unless otherwise noted
Symbol
Parameter
6 MHz
8 MHz
10 MHz
Unit Comments
-6 Min -6 Max -8 Min -8 Max -10 Min -10 Max
TCLCL
CLK Period
CKM e 1
CKM e 0
165 500 125 500
62 5 166 50 166
100
40
500 ns
166 ns
TCLCH
CLK LOW Time
CKM e 1
CKM e 0
100 343 68 343
15 146 15 146
53
11
343 ns At 0 8V
146 ns At 0 6V
TCHCL
CLK HIGH Time
CKM e 1
CKM e 0
50 230 43 230
20 151 20 151
28
18
230 ns At 2 0V
151 ns At 3 6V
TCH1CH2 CLK Rise Time
10 10
10 ns 1 0V to 3 6V
if CKM e 1
TCL2CL1 CLK Fall Time
10 10
10 ns 3 6V to 1 0V
if CKM e 1
TDVWH
TWHDX
TWLWH
TRLRH
TAVRL
TAVWL
TMHRL
Data Setup to NPWR Inactive
Data Hold from NPWR Inactive
NPWR NPRD Active Time
Command Valid to NPWR or
NPRD Active
Minimum Delay from PEREQ
Active to NPRD Active
75
30
95
0
130
75
18
90
0
130
75
18
90
0
100
ns
ns
ns At 0 8V
ns
ns
TKLKH
TKHKL
TKHCH
PEAK Active Time
PEAK Inactive Time
PEAK Inactive to NPWR
NPRD Inactive
85
250
50
85
250
40
60
200
40
ns At 0 8V
ns At 2 0V
ns
TCHKL NPWR NPRD Inactive to
PEAK Inactive
b30
b30
b30
ns
TWHAX Command Hold from NPWR
30
30
22
ns
TRHAX NPRD Inactive
TKLCL PEAK Active Setup to NPWR 50
40
40
ns
NPRD Active
TIVCL NPWR NPRD RESET
70
70
53
ns
to CLK Setup Time
TCLIH NPWR NPRD RESET
45
45
37
ns
from CLK Hold Time
TRSCL RESET to CLK Setup Time
20
20
20
ns
TCLRS RESET from CLK Hold Time
20
20
20
ns
NOTE
Tja e 41 C W
Tjc e 14 C W
5
5 Page 
M80287
SYSTEM CONFIGURATION WITH
M80286
As a processor extension to an M80286 the
M80287 can be connected to the CPU as shown in
Figure 4 The data channel control signals (PEREQ
PEACK) the BUSY signal and the NPRD NPWR
signals allow the NPX to receive instructions and
data from the CPU When in the protected mode all
information received by the NPX is validated by the
M80286 memory management and protection unit
Once started the M80287 can process in parallel
with and independent of the host CPU When the
NPX detects an error or exception it will indicate this
to the CPU by asserting the ERROR signal
The NPX uses the processor extension request and
acknowledge pins of the M80286 CPU to implement
data transfers with memory under the protection
model of the CPU The full virtual and physical ad-
dress space of the M80286 is available Data for the
M80287 in memory is addressed and represented in
the same manner as for an M8087
The M80287 can operate either directly from the
CPU clock or with a dedicated clock For operation
with the CPU clock (CKM e 0) the M80287 works
at one-third the frequency of the system clock (i e
for an 8 MHz M80286 the 16 MHz system clock is
divided down to 5 3 MHz) The M80287 provides a
capability to internally divide the CPU clock by three
to produce the required internal clock (33% duty cy-
cle) To use a higher performance M80287 (8 MHz)
an M8284A clock driver and appropriate crystal may
be used to directly drive the M80287 with a duty
cycle clock on the CLK input (CKM e 1)
SYSTEM CONFIGURATION WITH
M80386
The M80287 can also be connected as a processor
extension to the M80386 CPU as shown in Figure
4b All software written for M8086 M8087 and
M80286 M80287 is object code compatible with
80386 M80287 and can benefit from the increased
speed of the M80386 CPU
Note that the PEACK input pin is pulled high This is
because the M80287 is not required to keep track of
the number of words transferred during an operand
transfer when it is connected to the M80386 CPU
Unlike the M80286 CPU the M80386 CPU knows
the exact length of the operand being transferred
to from the M80287 After an ESC instruction has
been sent to the M80287 the M80386 processor
extension data channel will initiate the data transfer
as soon as it receives the PEREQ signal from the
M80287 The transfer is automatically terminated by
the M80386 CPU as soon as all the words of the
operand have been transferred
Because of the very high speed local bus of the
M80386 CPU the M80287 cannot reside directly on
the CPU local bus A local bus controller logic is
used to generate the necessary read and write cycle
timing as well as the chip select timings for the
M80287 The M80386 CPU uses I O addresses
800000F8 through 800000FF to communicate with
the M80287 This is beyond the normal I O address
space of the CPU and makes it easier to generate
the chip select signals using A31 and M IO It may
also be noted that the M80386 CPU automatically
generates 16-bit bus cycles whenever it communi-
cates with the M80287
HARDWARE INTERFACE
Communication of instructions and data operands
between the M80286 and M80287 is handled by the
CMD0 CMD1 NPS1 NPS2 NPRD and NPWR sig-
nals I O port addresses 00F8H 00FAH and 00FCH
are used by the M80286 for this communication
When any of these addresses are used the NPS1
input must be LOW and NPS2 input HIGH The
IORC and IOWC outputs of the M82288 identify I O
space transfers (see Figure 4) CMD0 should be
connected to latched M80286 A1 and CMD1 should
be connected to latched M80286 A2
I O ports 00F8H to 00FFH are reserved for the
M80286 M80287 interface To guarantee correct
operation of the M80287 programs must not per-
form any I O operations to these ports
The PEREQ PEACK BUSY and ERROR signals of
the M80287 are connected to the same-named
M80286 input The data pins of the M80287 should
be directly connected to the M80286 data bus Note
that all bus drivers connected to the M80286 local
bus must be inhibited when the M80286 reads from
the M80287 The use of COD INTA and M IO in the
decoder prevents INTA bus cycles from disabling
the data transceivers
The S1 S0 COD INTA READY HLDA and CLK
pins of the M80286 are connected to the same
named pins on the M80287 These signals allow the
M80287 to monitor the execution of ESCAPE in-
structions by the M80826
PROGRAMMING INTERFACE
Table 2 lists the seven data types the M80287 sup-
ports and presents the format for each type These
values are stored in memory with the least signifi-
cant digits at the lowest memory address Programs
retrieve these values by generating the lowest ad-
dress All values should start at even addresses for
maximum system performance
11
11 Page | ||
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