PDF M82510 Data sheet ( Hoja de datos )

Número de pieza	M82510
Descripción	ASYNCHRONOUS SERIAL CONTROLLER
Fabricantes	Intel
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M82510 ASYNCHRONOUS SERIAL CONTROLLER Military Y Asynchronous Operation 5- to 9-Bit Character Format Baud Rate DC to 288k Complete Error Detection Y Multiple Sampling Windows Y Two Independent Four-Byte Transmit and Receive FIFOs Programmable Threshold Y Two 16-bit Baud Rate Generators Timers Y System Clock Options On-Chip Crystal Oscillator External Clocks Y MCS -51 9-Bit Protocol Support Y Control Character Recognition Y CHMOS III with Power Down Mode Y Interrupts Maskable at Two Levels Y Auto Echo and Loopback Modes Y Seven I O Pins Dedicated and General Purpose Y Available in 28-Lead CERDIP and 28-Pad LCC Packages Y Military Temperature Range b55 C to a125 C (TC) The Intel CHMOS M82510 is designed to increase system efficiency in asynchronous environments such as modems serial ports including expanding performance areas MCS -51 9-bit format and high speed async The functional support provided in the M82510 is unparalleled 2 baud rate generators timers provide inde- pendent data rates or protocol timeouts a crystal oscillator and smart modem I O simplify system logic New features dual FIFOs and Control Character Recognition (CCR) dramatically reduce CPU interrupts and in- crease software efficiency The M82510’s software versatility allows emulation of the INS 8250A 16450 for IBM PC AT compatibility or a high performance mode configured by 35 control registers All interrupts are maskable at 2 levels The multi-personality I O pins are configurable as desired A DPLL and multiple sampling of serial data improve data reliability for high speed asynchronous communication The compact 28-pin M82510 is fabricated in CHMOS III technology and includes a software powerdown option IBM and PC AT are registered trademarks of IBM Corporation Figure 1 Block Diagram 271072 – 1 Other brands and names are the property of their respective owners Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or copyright for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products Intel retains the right to make changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata COPYRIGHT INTEL CORPORATION 1996 March 1996 Order Number 271072-007 1 page M82510 8250 Compatibility Upon power up or reset the M82510 comes up in the default wake up mode The 8250A 16450 compatible bank bank zero is the accessible bank and all the other registers are configured via their default values to support this mode Address 00 (DLAB e 0) 01 (DLAB e 0) 00 (DLAB e 1) 01 (DLAB e 1) 02 03 04 05 06 07 Table 3 8250A 16450 Compatible Registers M82510 Registers (Bank 0) 8250A Registers Read Write Read Write RxD TxD RBR THR GER GER IER IER BAL BAL DLL DLL BAH BAH DLM DLM GIR BANK BANK IIR LCR LCR LCR LCR MCR MCR MCR MCR LSR LSR LSR LSR MSR MSR MSR MSR ACR0 ACR0 SCR SCR RxD TxD BAL BAH GER GIR BANK LCR MCR LSR MSR ACR0 RST 02H 00H 00H 01H 00H 00H 60H 00H 00H 00H Table 4 Default Wake-Up Mode ACR1 00H RIE 1EH RMD 00H CLCF 00H BACF 04H BBCF 84H PMD FCH MIE 0FH TMIE 00H BBL 05H BBH 00H RxF TxF TMST TMCR FLR RCM TCM GSR ICM FMD TMD IMD 30H 00H 12H 00H 00H 0CH 5 5 Page M82510 Table 7 Standard Baud Rates Bit Rate 16x Divisor 110 5236 (1474h) 300 1 920 (780h) 1200 480 (1E0h) 2400 240 (F0h) 9600 60 (3Ch) 19 200 30 (1Eh) 38 400 15 (0Fh) 56 000 10 (0Ah) 288 000 2 (02h) Source CLK e Internal Sys Clk e 18 432 MHz 2 e 9 216 MHz % Error 007% 2 8% The BRG counts down in increments of two and then is divided by two to generate a 50% duty cycle however for odd divisors it will count down the first time by one All subsequent countdowns will then continue in steps of two In those cases the duty cycle is no longer exactly 50% The deviation is giv- en by the following equation deviation e 1 (2 X divisor) The BRG can operate with any divisor between 1 and 65 535 however for divisors between 1 and 3 the duty cycle is as follows Table 8 Duty Cycles Divisor Duty Cycle 3 33% 2 50% 1 Same as Source 0 FORBIDDEN Timer Mode Each of the M82510 BRGs can be used as Timers The Timer is used to generate time delays by count- ing the internal system clock When enabled the Timer uses the count from the Divisor Count regis- ters to count down to 1 Upon terminal count a maskable Timer Expired interrupt is generated The delay between the trigger and the terminal count is given by the following equation Delay e Count X (System Clock Period) To start counting the Timer has to be triggered via the Start Timer Command To restart the Timer after terminal count or while counting the software has to issue the trigger command again While counting the Timer can be enabled or disabled by using a soft- ware controlled Gate It is also possible to output a pulse generated upon terminal count through the TA or TB pins In 1X clock mode the only clock source available is the SCLK pin The serial machines (both Tx Machine and Rx Machine) can independently use one of two clock modes either 1X or 16X Also no configuration changes are allowed during operation as each write in the BRG configuration registers causes a reset signal to be sent to the BRG logic The mode or source clocks may be changed only after a Hard- ware or Software reset The Divisor (or count de- pending upon the mode) may be updated during op- eration unless the particular BRG machine is being used as a clock source for one of the serial ma- chines and the particular serial machine is in opera- tion at the time Loading the count registers with ‘‘0’’ is forbidden in all cases and loading it with a ‘‘1’’ is forbidden in the Timer Mode only SERIAL DIAGNOSTICS The M82510 supports two modes of Loopback oper- ation Local Loopback and Remote Loopback as well as an Echo mode for diagnostics and improved throughput LOCAL LOOPBACK 271072 – 11 Figure 12 Local Loopback The Tx Machine output and Rx Machine input are shorted internally TXD pin output is held at Mark This feature allows simulation of Transmission Re- ception of characters and checks the Tx FIFO Tx Machine Rx Machine and Rx FIFO along with the software without any external side effects The mo- dem outputs OUT1 OUT2 DTR and RTS are inter- nally shorted to RI DCD DSR and CTS respectively OUT0 is held at a mark state 11 11 Page

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