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PDF MK2049-34A Data sheet ( Hoja de datos )
| Número de pieza | MK2049-34A | |
| Descripción | 3.3 Volt Communications Clock VCXO PLL | |
| Fabricantes | Integrated Circuit Systems | |
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MK2049-34A
3.3 Volt Communications Clock VCXO PLL
Description
The MK2049-34A is a VCXO Phased Locked Loop
(PLL) based clock synthesizer that accepts multiple
input frequencies. With an 8 kHz clock input as a
reference, the MK2049-34A generates T1, E1, T3, E3,
ISDN, xDSL, and other communications frequencies.
This allows for the generation of clocks
frequency-locked and phase-locked to an 8 kHz
backplane clock, simplifying clock synchronization in
communications systems. The MK2409-34 can also
accept a T1 or E1 input clock and provide the same
output for loop timing. All outputs are frequency locked
together and to the input.
This part also has a jitter-attenuated Buffer capability.
In this mode, the MK2049-34A is ideal for filtering jitter
from 27 MHz video clocks or other clocks with high
jitter.
ICS can customize these devices for many other
different frequencies.
Features
• Packaged in 20-pin SOIC
• 3.3 V + 5% operation
• Fixed I/O phase relationship on all selections
• Meets the TR62411, ETS300 011, and GR-1244
specification for MTIE, Pull-in/Hold-in Range, Phase
Transients, and Jitter Generation for Stratum 3, 4,
and 4E
• Accepts multiple inputs: 8 kHz backplane clock, Loop
Timing frequencies, or 10 to 36 MHz
• Locks to 8 kHz + 100 ppm (External mode)
• Buffer Mode allows jitter attenuation of 10 to 36 MHz
input and x1/x0.5 or x2/x4 outputs
• Exact internal ratios enable zero ppm error
• Output clock rates include T1, E1, T3, E3, ISDN,
xDSL, and the OC3 submultiples
• See the MK2049-01, -02, and -03 for more selections
at 5 V
Block Diagram
INPUT REFERENCE
CLOCK
(TYPICALLY 8KHZ)
4
FREQUENCY SELECT
EXTERNAL PULLABLE CRYSTAL
(external loop filter)
VCXO-BASED
PLL
(MASTER CLOCK
GENERATOR)
FREQUENCY
MULTIPLYING
PLL
2
CLOCK OUTPUT
CLOCK OUTPUT / 2
8 KHZ (REGENERATED)
MDS 2049-34A A
1
Revision 032504
Integrated Circuit Systems, Inc. z 525 Race Street, San Jose, CA 95126 z tel (408) 297-1201 z www.icst.com
1 page  
MK2049-34A
3.3 Volt Communications Clock VCXO PLL
PC Board Layout
A proper board layout is critical to the successful use of the MK2049-34A. In particular, the CAP1 and CAP2 pins
are very sensitive to noise and leakage (CAP2 at pin 18 is the most sensitive). Traces must be as short as possible
and the two capacitors and resistor must be mounted next to the device as shown below. The capacitor shown
between pins 15 and 17, and the one between pins 4 and 7 are the power supply decoupling capacitors. The high
frequency output clocks on pins 8 and 9 should have a series termination of 33Ω connected close to the pin.
Additional improvements will come from keeping all components on the same side of the board, minimizing vias
through other signal layers, and routing other signals away from the MK2049. You may also refer to application note
MAN05 for additional suggestions on layout of the crystal selection.
The crystal traces should include pads for small capacitors from X1 and X2 to ground. These are used to adjust the
stray capacitance of the board to match the crystal load capacitance. The typical telecom reference frequency is
accurate to much less than 1 ppm, so the MK2049-34A may lock and run properly even if the board capacitance is
not adjusted with these fixed capacitors. However, ICS recommends that the adjustment capacitors be included to
minimize the effects of variation in individual crystals, temperature, and aging. The value of these capacitors
(typically 0 - 4 pF) is determined once for a given board layout, using the procedure found in application note
MAN05 (http://www.icst.com/products/summary/man05.htm).
Optional -
see text G
cap
V
resist
resist
Cutout in ground and power plane.
Route all traces away from this area.
1 20
2
19 resist
G
3 18
resist
4 17 G
5 16
cap
6 15 V
7 14
8 13
9 12
V = connect to VDD
10 11
G = connect to GND
Figure 2. Typical MK2049-34 Layout
MDS 2049-34A A
5
Revision 032504
Integrated Circuit Systems, Inc. z 525 Race Street, San Jose, CA 95126 z tel (408) 297-1201 z www.icst.com
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet MK2049-34A.PDF ] | |
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