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PDF 82503 Data sheet ( Hoja de datos )
| Número de pieza | 82503 | |
| Descripción | DUAL SERIAL TRANSCEIVER (DST) | |
| Fabricantes | Intel Corporation | |
| Logotipo |  |
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82503
DUAL SERIAL TRANSCEIVER (DST)
82503 PRODUCT FEATURE SET OVERVIEW
Y Single Component Ethernet Interface
to Both 802 3 10BASE-T and AUI
Y Automatic or Manual Port Selection
Y Manchester Encoder Decoder and
Clock Recovery
Y No Glue Interface to Industry-Standard
LAN Controllers
Intel 82586 82590 82593 and 82596
AMD 7990 (LANCE )
National Semiconductor 8390 and
83932 (SONIC )
Western Digital 83C690
Fujitsu 86950 (Etherstar )
Y Diagnostic Loopback
Y Reset Low Power Modes
Y Network Status Indicators
Y Defeatable Jabber Timer
Y User Test Modes
Y 10 MHz Transmit Clock Generator
Y One Micron CHMOS IV (Px48)
Technology
Y Single 5-V Supply
INTERFACE FEATURES
TPE
Y Complies with 10BASE-T IEEE Std
802 3i-1990 for Twisted Pair Ethernet
Y Selectable Polarity Switching
Y Direct Interface to TPE Analog Filters
Y On-Chip TPE Squelch
Y Defeatable Link Integrity (LI)
Y Support of Cable Lengths l100m
AUI
Y Complies with IEEE 802 3 AUI Standard
Y Direct Interface to AUI Transformers
Y On-Chip AUI Squelch
A block diagram of a typical application is shown in Figure 1 The 82503 Dual Serial Transceiver is a high-inte-
gration CMOS device designed to simplify interfacing industry standard Ethernet LAN Controllers to IEEE
802 3 local area network applications (10BASE5 10BASE2 and 10BASE-T) The component supports both
an attachment unit interface (AUI) and a Twisted Pair Ethernet interface (TPE) It allows OEMs to design a
state-of-the-art media interface that is jumperless and fully automatic The 82503 includes on-chip AUI and
TPE drivers and receivers it offers designers a cost-effective integrated solution for interfacing LAN control-
lers to the wire medium
CHMOS is a patented process of Intel Corporation
Ethernet is a registered trademark of Xerox Corporation
LANCE is a registered trademark of Advanced Micro Devices
Etherstar is a registered trademark of Fujitsu Electronics
Sonic is a registered trademark of National Semiconductor Corporation
Other brands and names are the property of their respective owners
Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or
copyright for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products Intel retains the right to make
changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata
COPYRIGHT INTEL CORPORATION 1996
October 1995
Order Number 290421-004
1 page  
2 0 PIN DEFINITION
82503
Figure 3 44-Lead PLCC Pin Configuration
290421 – 3
Figure 4 44-Lead QFP Pin Configuration
290421 – 44
5
5 Page 
82503
Figure 5 TPE Predistortion
290421 – 4
3 3 Receive Blocks
3 3 1 MANCHESTER DECODER AND CLOCK
RECOVERY
The 82503 performs Manchester decoding and tim-
ing recovery of the incoming data in AUI and TPE
modes
The Manchester-encoded data stream is decoded to
separate the Receive Clock (RxC) and the Receive
Data (RxD) from the differential signal The 82503
uses an advanced digital technique to perform the
decoding function The use of digital circuitry instead
of analog circuitry (e g a phase-lock loop) to per-
form the decoding ensures that the decoding func-
tion is less sensitive to variations in operating condi-
tions
A high-resolution phase reference is used to digitize
the phase of the incoming data bit-center transition
The digitizer has a phase resolution of 1 32 of a bit
time
The digitized phase is filtered by a digital low-pass
filter to remove rapid phase variations i e phase
jitter Slow phase variations such as those caused
by small differences between the data frequency
and the clock frequency are not filtered by the low-
pass filter
The RxC generator digitally sets the phases of the
two RxC transitions to respectively lead and lag the
bit-center transition by bit time RxC is used to
recover RxD by sampling the incoming data with an
edge-triggered flip-flop
Lock is achieved by reducing the time constant of
the digital filter to zero at the start of a new frame
Any uncertainty in the bit-center phase of the first
transition that is caused by jitter is subsequently re-
moved by gradually increasing the filter time con-
stant during the following preamble By that time the
phase of the bit center is output by the filter and
lock is achieved Lock is achieved within the first 14
bit times as seen by the AUI inputs The maximum
bit-cell timing distortion (jitter) tolerated by the Man-
chester decoder circuitry is g12 ns (preamble)
g18 ns (data) for AUI and g13 5 ns for TPE (data
and preamble)
11
11 Page | ||
| Páginas | Total 45 Páginas | |
| PDF Descargar | [ Datasheet 82503.PDF ] | |
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