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Fairchild - 2K/4K/8K/16K-Bit Standard 2-Wire Bus Interface Serial EEPROM with Full Array Write Protect

Numéro de référence NM24W04
Description 2K/4K/8K/16K-Bit Standard 2-Wire Bus Interface Serial EEPROM with Full Array Write Protect
Fabricant Fairchild 
Logo Fairchild 





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NM24W04 fiche technique
PRELIMINARY
March 1999
NM24Wxx
2K/4K/8K/16K-Bit Standard 2-Wire Bus Interface
Serial EEPROM with Full Array Write Protect
General Description
The NM24Wxx devices are 2048/4096/8192/16,384 bits, respec-
tively, of CMOS non-volatile electrically erasable memory. These
devices conform to all specifications in the IIC 2-wire protocol and
are designed to minimize device pin count, and simplify PC board
layout requirements.
The entire ememory can be disabled (Write Protected) by con-
necting the WP pin to VCC. The memory then becomes unalterable
unless WP is switched to VSS.
This communications protocol uses CLOCK (SCL) and DATA
I/O (SDA) lines to synchronously clock data between the master
(for example a microprocessor) and the slave EEPROM device(s).
The Standard IIC protocol allows for a maximum of 16K of
EEPROM memory which is supported by Fairchild's family in 2K,
4K, 8K, and 16K devices, allowing the user to configure the
memory as the application requires with any combination of
EEPROMs.
Fairchild EEPROMs are designed and tested for applications
requiring high endurance, high reliability and low power consump-
tion.
Features
s Hardware Write Protect for entire memory
s Low Power CMOS
200µA active current typical
10µA standby current typical
1µA standby typical (L)
0.1µA standby typical (LZ)
s IIC Compatible interface
— Provides bidirectional data transfer protocol
s Sixteen byte page write mode
— Minimizes total write time per byte
s Self timed write cycle
— Typical write cycle time of 6ms
s Endurance: 1,000,000 data changes
s Data retention greater than 40 years
s Packages available: 8-pin DIP, 8-pin SO, and 8-pin TSSOP
s Available in three temperature ranges
- Commercial: 0° to +70°C
- Extended (E): -40° to +85C
- Automotive (V): -40° to +125°C
Block Diagram
VCC
VSS
WP
SDA
SCL
A2
A1
A0
START
STOP
LOGIC
START CYCLE
H.V. GENERATION
TIMING &CONTROL
SLAVE ADDRESS
REGISTER &
COMPARATOR
CONTROL
LOGIC
LOAD
INC
WORD
ADDRESS
COUNTER
R/W
XDEC
16/
32/
64/
128/
0/1/2/3
4
4
E2PROM
ARRAY
16
YDEC
Device Address Bits
DIN
8
CK
DATA REGISTER
DOUT
© 1999 Fairchild Semiconductor Corporation
NM24Wxx Rev. C.2
1
DS500074-1
www.fairchildsemi.com

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