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PDF NM25C020 Data sheet ( Hoja de datos )
| Número de pieza | NM25C020 | |
| Descripción | 2K-Bit Serial CMOS EEPROM (Serial Peripheral Interface (SPI) Synchronous Bus) | |
| Fabricantes | Fairchild | |
| Logotipo |  |
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March 1999
NM25C020
2K-Bit Serial CMOS EEPROM
(Serial Peripheral Interface (SPI) Synchronous Bus)
General Description
Features
The NM25C020 is a 2048-bit CMOS EEPROM with an SPI
compatible serial interface. The NM25C020 is designed for data
storage in applications requiring both non-volatile memory and in-
system data updates. This EEPROM is well suited for applications
using the 68HC11 series of microcontrollers that support the SPI
interface for high speed communication with peripheral devices
via a serial bus to reduce pin count. The NM25C020 is imple-
mented in Fairchild Semiconductor’s floating gate CMOS process
that provides superior endurance and data retention.
The serial data transmission of this device requires four signal
lines to control the device operation: Chip Select (CS), Clock
(SCK), Data In (SI), and Serial Data Out (SO). All programming
cycles are completely self-timed and do not require an erase
before WRITE.
BLOCK WRITE protection is provided by programming the STA-
TUS REGISTER with one of four levels of write protection.
Additionally, separate WRITE enable and WRITE disable instruc-
tions are provided for data protection.
s 2.1 MHz clock rate @ 2.7V to 5.5V
s 2048 bits organized as 256 x 8
s Multiple chips on the same 3-wire bus with separate chip
select lines
s Self-timed programming cycle
s Simultaneous programming of 1 to 4 bytes at a time
s Status register can be polled during programming to monitor
READY/BUSY
s Write Protect (WP) pin and write disable instruction for both
hardware and software write protection
s Block write protect feature to protect against accidental
writes
s Endurance: 1,000,000 data changes
s Data retention greater than 40 years
s Packages available: 8-pin DIP, 8-pin SO, or 8-pin TSSOP
Hardware data protection is provided by the WP pin to protect
against inadvertent programming. The HOLD pin allows the serial
communication to be suspended without resetting the serial
sequence.
Block Diagram
CS
HOLD
SCK
SI
Instruction
Register
Instruction
Decoder
Control Logic
and Clock
Generators
VCC
VSS
WP
Address
Counter/
Register
Decoder
1 of 256
Program
Enable
VPP
EEPROM Array
2048 Bits
(256 x 8)
High Voltage
Generator
and
Program
Timer
Read/Write Amps
Data In/Out Register
8 Bits
Data Out
Buffer
SO
Non-Volatile
Status Register
DS012400-1
© 1999 Fairchild Semiconductor Corporation
NM25C020 Rev. D.1
1
www.fairchildsemi.com
1 page  
AC Test Conditions (Continued)
FIGURE 1. Synchronous Data Timing Diagram
VIH
CS
VIL
tCSS
VIH
SCK
VIL
VIH
,,SI
VIL
VOH
SO
,VOL
tCLH
tCLL
tDIS
tPD
tDIN
tDH
tCSH
tCSN
tDF
FIGURE 2. HOLD Timing
SCK
HOLD
tHDS
SO
tHDN
tHZ
tHDS
tHDN
tLZ
FIGURE 3. SPI Serial Interface
MASTER MCU
DATA OUT (MOSI)
DATA IN (MISO)
SERIAL CLOCK (CLK)
SPI
SS0
CHIP
SS1
SELECTION SS2
SS3
NM25C020 Rev. D.1
5
NM25C020
SI
SO
SCK
CS
SI
SO
SCK
CS
SI
SO
SCK
CS
SI
SO
SCK
CS
DS012400-3
DS012400-6
DS012400-4
www.fairchildsemi.com
5 Page | ||
| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet NM25C020.PDF ] | |
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