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PDF 8840 Data sheet ( Hoja de datos )
| Número de pieza | 8840 | |
| Descripción | In-System Programmable SuperBIG High Density PLD | |
| Fabricantes | Lattice Semiconductor | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de 8840 (archivo pdf) en la parte inferior de esta página. Total 23 Páginas | ||
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ispLSI® 8840
In-System Programmable
SuperBIG™ High Density PLD
Features
• SuperBIG HIGH DENSITY IN-SYSTEM
PROGRAMMABLE LOGIC
— 5V Power Supply
— 45,000 PLD Gates/840 Macrocells
— Up to 312 I/O Pins Supporting 3.3V/5V I/O
— 1152 Registers
— High-Speed Global and Big Fast Megablock (BFM)
Interconnect
— Wide 20-Macrocell Generic Logic Block (GLB) for
High Performance
— Wide Input Gating (44 Inputs per GLB) for Fast
Counters, State Machines, Address Decoders, Etc.
— PCB-Efficient Ball Grid Array (BGA) Package
Options
• HIGH-PERFORMANCE E2CMOS® TECHNOLOGY
— fmax = 110 MHz Maximum Operating Frequency
— tpd = 8.5 ns Propagation Delay
— TTL Compatible Inputs and 3.3V/5V Outputs
— PCI Compatible Inputs, Outputs and Speed Grades
— Electrically Erasable and Reprogrammable
— Non-Volatile
— Programmable Speed/Power Logic Path
Optimization
• IN-SYSTEM PROGRAMMABLE
— Increased Manufacturing Yields, Reduced Time-to-
Market and Improved Product Quality
— Reprogram Soldered Devices for Faster Debugging
• 100% IEEE 1149.1 BOUNDARY SCAN TESTABLE AND
5V IN-SYSTEM PROGRAMMABLE
• ARCHITECTURE FEATURES
— Enhanced Pin-Locking Architecture, Symmetrical
Generic Logic Blocks Connected by Hierarchical
Big Fast Megablock and Global Routing Planes
— Product Term Sharing Array Supports up to 28
Product Terms per Macrocell Output
— Macrocells Support Concurrent Combinatorial and
Registered Functions
— Embedded Tristate Bus Can Be Used as an Internal
Tristate Bus or as an Extension of an External
Tristate Bus
— Macrocell and I/O Registers Feature Multiple Control
Options, Including Set, Reset and Clock Enable
— I/O Pins Support Programmable Bus Hold, Pull-Up,
Open-Drain and Slew Rate Options
— Separate VCCIO Power Supply for Output Drivers
Supports 5V or 3.3V Outputs
— I/O Cell Register Programmable as Input Register for
Fast Setup Time or Output Register for Fast Clock to
Output Time
• ispDesignEXPERT™ – LOGIC COMPILER AND COM-
PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL
SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING
— Superior Quality of Results
— Tightly Integrated with Leading CAE Vendor Tools
— Productivity Enhancing Timing Analyzer, Explore
Tools, Timing Simulator and ispANALYZER™
— PC and UNIX Platforms
Functional Block Diagram
12 12 12 12 12 12
I/O I/O I/O I/O I/O I/O
12
I/O
Big Fast Megablock 0
12
I/O
12
I/O
Big Fast Megablock 1
12
I/O
12
I/O
Big Fast Megablock 2
Global Routing Plane
12
I/O
Big Fast Megablock 3
12
I/O
12
I/O
12
I/O
Big Fast Megablock 4
12
I/O
12
I/O
Big Fast Megablock 5
12
I/O
12
I/O
Big Fast Megablock 6
12
I/O
Boundary
Scan
12 12 12 12 12 12
I/O I/O I/O I/O I/O I/O
8840 block
ispLSI 8000 Family Description
The ispLSI 8000 Family of Register-Intensive, SuperBIG
In-System Programmable Logic Devices is based on Big
Fast Megablocks of 120 registered macrocells and a
Global Routing Plane (GRP) structure interconnecting
the Big Fast Megablocks. Each Big Fast Megablock
contains 120 registered macrocells arranged in six groups
of 20, a group of 20 being referred to as a Generic Logic
Block, or GLB. Within the Big Fast Megablock, a Big Fast
Megablock Routing Pool (BRP) interconnects the six
GLBs to each other and to 24 Big Fast Megablock I/O
Copyright © 2000 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
January 2000
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
8840_07
1
1 page  
Specifications ispLSI 8840
Figure 2. ispLSI 8000 GLB Overview
I/O Big Fast Megablock Input Tracks
0
PT 0
PT 1
PT 2
PT 3
AND Array Input
Routing
General Purpose Big Fast Megablock Input Tracks
Feedback Inputs
43
20
Product Term
Sharing Array
PT 4
PT 5
PT 6
PT 7
PT 8
PT 9
PT 10
PT 11
PT 12
PT 13
PT 14
PT 15
Fully Populated
AND Array
Macrocell 0
From PTSA
PTSA Bypass
Single PT
PT Clock
PT Preset
PT Reset
Shared PT Clock
Bus Input
0
To Interconnect
Macrocell 1
From PTSA
PTSA Bypass
Single PT
PT Clock
PT Preset
PT Reset
Shared PT Clock
Bus Input
1
From Tristate
Bus Track
To Interconnect
Macrocell 2
From PTSA
PTSA Bypass
Single PT
PT Clock
PT Preset
PT Reset
Shared PT Clock
Bus Input
From Tristate
Bus Track
To Interconnect
2
Macrocell 3
From PTSA
PTSA Bypass
Single PT
PT Clock
PT Preset
PT Reset
Shared PT Clock
Bus Input
From Tristate
Bus Track
To interconnect
3
From Tristate
Bus Track
PT 76
PT 77
PT 78
PT 79
PT 80
PT 81
Note: Macrocells 9 and 10 do not support Tristate Bus Feedback.
5
Macrocell 19
From PTSA
PTSA Bypass
Single PT
PT Clock
PT Preset
PT Reset
Shared PT Clock
Bus Input
19
To Interconnect
From Tristate Bus Track
To Output Control MUX
Function Selector (E2 Cell Controlled)
5 Page 
Specifications ispLSI 8840
Absolute Maximum Ratings 1,2
Supply Voltage Vcc .................................. -0.5 to +7.0V
Input Voltage Applied ........................ -2.5 to VCC +1.0V
Tri-Stated Output Voltage Applied .... -2.5 to VCC +1.0V
Storage Temperature ................................ -65 to 150°C
Case Temp. with Power Applied .............. -55 to 125°C
Max. Junction Temp. (TJ) with Power Applied ... 140°C
1. Stresses above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional
operation of the device at these or at any other conditions above those indicated in the operational sections of this specification
is not implied (while programming, follow the programming specifications).
2. Compliance with the Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM is a requirement.
DC Recommended Operating Condition
SYMBOL
VCC
VCCIO
VIH
VIL
VOH
VOL
Supply Voltage
Output Supply Voltage
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
PARAMETER
Commercial TA = 0°C to 70°C
Capacitance (TA=25°C,f=1.0 MHz)
MIN.
4.75
3.0
2.0
0.0
2.4
—
MAX. UNITS
5.25 V
5.25 V
VCC +1
0.8
V
V
—V
0.4 V
Table 2-0005/8840
SYMBOL
C1
C2
C3
PARAMETER
I/O Capacitance
Clock Capacitance
Global Input Capacitance
Erase/Reprogram Specification
TYPICAL
10
10
10
UNITS
pf
pf
pf
TEST CONDITIONS
VCC = 5.0V, VI/O = 2.0V
VCC = 5.0V, VCK = 2.0V
VCC = 5.0V, VG = 2.0V
Table 2-0006/8840
PARAMETER
ispLSI Erase/Reprogram Cycles
MINIMUM
10000
MAXIMUM
–
UNITS
Cycles
Table 2-0008/3320
11
11 Page | ||
| Páginas | Total 23 Páginas | |
| PDF Descargar | [ Datasheet 8840.PDF ] | |
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