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PDF NS32FX16-25 Data sheet ( Hoja de datos )
| Número de pieza | NS32FX16-25 | |
| Descripción | Imaging/Signal Processor | |
| Fabricantes | National | |
| Logotipo |  |
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PRELIMINARY
July 1991
NS32FX16-15 NS32FX16-20 NS32FX16-25
Imaging Signal Processor
General Description
The NS32FX16 is a high-performance 32-bit member of the
Series 32000 EPTM family of National’s Embedded System
ProcessorsTM specifically optimized for CCITT Group 2 and
Group 3 Facsimile Applications Data Modems Voice Mail
Systems Laser Printers or any combination of the above
It can perform all the computations and control functions
required for a stand-alone Fax system a PC add-in Fax
Data Modem card or a Laser Fax system
It also meets the performance requirements to implement
9600 and 7200 bps modems complying with CCITT V 29
and V 27 standards
The NS32FX16 provides a 16 Mbyte Linear external ad-
dress space and a 16-bit external data bus
The CPU core which is the same as that of the NS32CG16
incorporates a 32-bit ALU and instruction pipeline and an
8-byte prefetch queue
Also integrated on-chip with the CPU are a DSP Module and
a 384-byte RAM Array The DSP Module executes vector
operations on complex variables and is specially designed
to enhance performance in modem applications The vector
operations can also be used to efficiently implement FIR
Filters and other DSP primitives The on-chip RAM Array is
used to store the coefficients of the various filters and can
be accessed by both the CPU and the DSP Module
The NS32FX16 capabilities can be expanded by using an
external floating point unit (FPU) which directly interfaces to
the NS32FX16 using the slave protocol The CPU-FPU clus-
ter features high speed execution of the floating-point in-
structions
The NS32FX16 highly-efficient architecture combined with
the NS32CG16 graphics instructions and the high-perform-
ance vector operation capability makes the device the ideal
choice for PostscriptTM and Fax applications
Features
Y Software compatible with the Series 32000 EP
processors
Y Designed around the CPU core of the NS32CG16
Y 32-bit architecture and implementation
Y On-chip DSP Module for high-speed DSP operations
Y Special support for graphics applications
18 graphics instructions
Binary compression expansion capability for font
storage using RLL encoding
Pattern magnification
Interface to an external BITBLT processing units for
fast color BITBLT operations
Y 384-byte on-chip RAM array
Y On-chip clock generator
Y Floating-point support via the NS32081 or NS32181
Y Optimal interface to large memory arrays via the
NS32CG821 and the DP84xx family of DRAM control-
lers
Y Power save mode
Y High-speed CMOS technology
Y 68-pin PLCC package
Block Diagram
Series 32000 is a registered trademark of National Semiconductor Corporation
EPTM and Embedded System ProcessorsTM are trademarks of National Semiconductor Corporation
C1995 National Semiconductor Corporation TL EE10818
TL EE 10818 – 67
RRD-B30M115 Printed in U S A
1 page  
List of Illustrations (Continued)
Connection Diagram
Output Signals Specification Standard
Input Signals Specification Standard
Read Cycle
Write Cycle
Special Bus Cycle
HOLD Acknowledge Timing (Bus Initially Not Idle)
HOLD Timing (Bus Initially Idle)
External DMA Controller Bus Cycle
Slave Processor Write Timing
Slave Processor Read Timing
SPC Timing
PFS Signal Timing
ILO Signal Timing
Clock Waveforms
INT Signal Timing
NITI Signal Timing
Power-On Reset
Non-Power-On Reset
List of Tables
NS32FX16 Addressing Modes
NS32FX16 Instruction Set Summary
‘op’ and ‘i’ Field Encodings
Floating-Point Instruction Protocols
Summary of Exception Processing
DSPM Instructions Summary
Circular Buffer Sizes
External Oscillator Specifications
Interrupt Sequences
Bus Cycle Categories
Data Access Sequences
Basic Instructions
Floating-Point Instructions CPU Portion
Average Instruction Execution Times with No Wait-States
Average Instruction Execution Times with Wait-States
DSPM Instruction Execution Times
4-1
4-2
4-3
4-4
4-5
4-6
4-7
4-8
4-9
4-10
4-11
4-12
4-13
4-14
4-15
4-16
4-17
4-18
4-19
2-1
2-2
2-3
3-1
3-2
3-3
3-4
3-5
3-6
3-7
3-8
B-1
B-2
B-3
B-4
B-5
5
5 Page 
2 0 Architectural Description (Continued)
Address (Hex)
00000000
Memory and I O
00FFFE00
01000000
FF800000
FFFFD000
FFFFD200
FFFFD4XX
Interrupt Control
Address Not Available Off-Chip
(Do Not Use)
Reserved
On-Chip RAM Array
Reserved
DSP Module
FFFFFFFF
Reserved
FIGURE 2-9 NS32FX16 Address Mapping
2 3 MODULAR SOFTWARE SUPPORT
The NS32FX16 provides special support for software mod-
ules and modular programs
Each module in a NS32FX16 software environment consists
of three components
1 Program Code Segment
This segment contains the module’s code and constant
data
2 Static Data Segment
Used to store variables and data that may be accessed
by all procedures within the module
3 Link Table
This component contains two types of entries Absolute
Addresses and Procedure Descriptors
An Absolute Address is used in the external addressing
mode in conjunction with a displacement and the current
MOD Register contents to compute the effective address
of an external variable belonging to another module
The Procedure Descriptor is used in the call external pro-
cedure (CXP) instruction to compute the address of an
external procedure
Normally the linker program specifies the locations of the
three components The Static Data and Link Table typically
reside in RAM the code component can be either in RAM or
in ROM The three components can be mapped into non-
contiguous locations in memory and each can be indepen-
dently relocated Since the Link Table contains the absolute
addresses of external variables the linker need not assign
absolute memory addresses for these in the module itself
they may be assigned at load time
To handle the transfer of control from one module to anoth-
er the NS32FX16 uses a module table in memory and two
registers in the CPU
The Module Table is located within the first 64 kbytes of
memory This table contains a Module Descriptor (also
called a Module Table Entry) for each module in the ad-
dress space of the program A Module Descriptor has four
32-bit entries corresponding to each component of a mod-
ule
The Static Base entry contains the address of the begin-
ning of the module’s static data segment
The Link Table Base points to the beginning of the mod-
ule’s Link Table
The Program Base is the address of the beginning of the
code and constant data for the module
A fourth entry is currently unused but reserved
The MOD Register in the CPU contains the address of the
Module Descriptor for the currently executing module
The Static Base Register (SB) contains a copy of the Static
Base entry in the Module Descriptor of the currently execut-
ing module i e it points to the beginning of the current
module’s static data area
This register is implemented in the CPU for efficiency pur-
poses By having a copy of the static base entry or chip the
CPU can avoid reading it from memory each time a data
item in the static data segment is accessed
In an NS32FX16 software environment modules need not
be linked together prior to loading As modules are loaded
a linking loader simply updates the Module Table and fills
the Link Table entries with the appropriate values No modi-
fication of a module’s code is required Thus modules may
be stored in read-only memory and may be added to a sys-
tem independently of each other without regard to their in-
dividual addressing Figure 2-10 shows a typical NS32FX16
run-time environment
11
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