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PDF NS32FX164V-25 Data sheet ( Hoja de datos )
| Número de pieza | NS32FX164V-25 | |
| Descripción | Advanced Imaging/Communication Signal Processors | |
| Fabricantes | National | |
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February 1992
NS32FX161-15 NS32FX161-20 NS32FX164-20
NS32FX164-25 NS32FV16-20 NS32FV16-25
Advanced Imaging Communication Signal Processors
General Description
The NS32FX164 the NS32FV16 and the NS32FX161 are
high-performance 32-bit members of the Series 32000
EPTM family of National’s Embedded System ProcessorsTM
specifically optimized for CCITT Group 2 and Group 3 Fac-
simile Applications Data Modems Voice Mail Systems La-
ser Printers or any combination of the above
Unless specified otherwise any reference to the
NS32FX164 in this document applies to the NS32FV16 and
the NS32FX161 as well
The NS32FX164 can perform all the computations and con-
trol functions required for a stand-alone Fax system a PC
add-in Fax Voice Data Modem card or a Laser Fax sys-
tem
It also meets the performance requirements to implement
14400 9600 and 7200 bps modems complying with CCITT
V 17 V 29 and V 27 standards The NS32FV16 supports
V 29 and V 27 standards as well as voice The NS32FX161
supports V 29 and V 27 standards
The NS32FX164 provides a 16 Mbyte Linear external ad-
dress space and a 16-bit external data bus
The CPU core which is the same as that of the NS32CG16
incorporates a 32-bit ALU and instruction pipeline and an
8-byte prefetch queue
Also integrated on-chip with the CPU are a DSP Module
(DSPM) and a 4K-byte RAM Array (2K in the NS32FV16 and
NS32FX161) The DSPM is a complete processing unit ca-
pable of autonomous operation parallel to the CPU core
operation The DSPM executes programs stored in an inter-
nal on-chip Random Access Memory (RAM) and manipu-
lates data stored either in the internal RAM or in an external
off-chip memory To maximize utilization of hardware re-
sources the DSPM contains a pipelined DSP-oriented data-
path and a control logic that implements a set of DSP vec-
tor commands
The NS32FX164 capabilities can be expanded by using an
external floating point unit (FPU) which directly interfaces to
the NS32FX164 using the slave protocol The CPU-FPU
cluster features high speed execution of the floating-point
instructions
The NS32FX164 highly-efficient architecture combined with
the NS32CG16 graphics instructions and the high-perform-
ance vector operation capability makes the device the ideal
choice for PostscriptTM and Fax applications
Features
Y Software compatible with the Series 32000 EP
processors
Y Designed around the CPU core of the NS32CG16
Y Pin compatible with the NS32FX16
Y 32-bit architecture and implementation
Y On-chip DSP Module for high-speed DSP operations
Y Special support for graphics applications
18 graphics instructions
Binary compression expansion capability for font
storage using RLL encoding
Pattern magnification
Interface to an external BITBLT processing units for
fast color BITBLT operations
Y 4K-byte on-chip RAM array (2K in NS32FV16 and
NS32FX161)
Y On-chip clock generator
Y Floating-point support via the NS32081 or NS32181
Y Optimal interface to large memory arrays via the
NS32CG821 and the DP84xx family of DRAM
controllers
Y Power save mode
Y High-speed CMOS technology
Y 68-pin PLCC package
Block Diagram
FIGURE 1-1 CPU Block Diagram
Series 32000 is a registered trademark of National Semiconductor Corporation
EPTM and Embedded System ProcessorsTM are trademarks of National Semiconductor Corporation
PostscriptTM is a trademark of Adobe Systems Inc
C1995 National Semiconductor Corporation TL EE11267
TL EE 11267 – 1
RRD-B30M115 Printed in U S A
1 page  
FIGURE 4-17 NMI Signal Timing
FIGURE 4-18 Power-On Reset
FIGURE 4-19 Non-Power-On Reset
FIGURE 4-20 Interrupt Out
List of Figures (Continued)
List of Tables
TABLE 2-1 NS32FX164 Addressing Modes
TABLE 2-2 NS32FX164 Instruction Set Summary
TABLE 2-3 ‘op’ and ‘i’ Field Encodings
TABLE 3-1 Floating-Point Instruction Protocols
TABLE 3-2 Summary of Exception Processing
TABLE 3-3 External Oscillator Specifications Crystal Characteristics
TABLE 3-4 Interrupt Sequences
TABLE 3-5 Bus Cycle Categories
TABLE 3-6 Data Access Sequences
TABLE B-1 Basic Instructions
TABLE B-2 Floating-Point Instructions CPU Portion
TABLE B-3 Average Instruction Execution Times with No Wait-States
TABLE B-4 Average Instruction Execution Times with Wait-States
87
87
88
88
15
16
23
28
40
57
64
67
68
94
98
99
100
5
5 Page 
2 0 Architectural Description (Continued)
EXT External Memory Reference Control Register
The format of the external memory reference control regis-
ter is shown in Figure 2-11
15 1 0
Reserved
HOLD
FIGURE 2-11 EXT Register Format
The EXT register controls external references The com-
mand-list execution unit checks the value of EXT HOLD be-
fore each external memory reference When EXT HOLD is
‘‘0’’ external memory references are allowed When
EXT HOLD is ‘‘1’’ and external memory references are re-
quested the execution of the command list will stop until
EXT HOLD is ‘‘0’’ Upon reset and whenever the ABORT
register is written EXT HOLD is cleared to ‘‘0’’ The EXT
register can be read or written by the core
CLSTAT Command-List Execution Status Register
The format of the command-list execution status register is
shown in Figure 2-12
15 1 0
Reserved
RUN
FIGURE 2-12 CLSTAT Register Format
The CLSTAT register displays the current status of the exe-
cution of the command list When the command-list execu-
tion is idle CLSTAT RUN is ‘‘0’’ and when it is active
CLSTAT RUN is ‘‘1’’ Upon reset the CLSTAT register is
cleared to ‘‘0’’ It can only be read and only by the core
DSPINT DSPMASK NMISTAT Interrupt Control
Registers
The format of DSPINT and DSPMASK is shown in Figure
2-13
15 1 0
Reserved
HALT
FIGURE 2-13 DSPINT and DSPMASK Register Format
The DSPINT register holds the current status of interrupt
requests Whenever execution of the command list is
stopped the DSPINT HALT bit is set to ‘‘1’’ The DSPINT is
a read only register It is cleared to ‘‘0’’ whenever it is read
whenever the ABORT register is written and upon reset
The DSPMASK register is used to mask the DSPINT HALT
flag An interrupt request is transferred to the interrupt logic
of the IOUT output pin whenever the DSPINT HALT bit is
set to ‘‘1’’ and the DSPMASK HALT bit is unmasked (set to
‘‘1’’) See Section 4 0 for the functionality of IOUT
DSPMASK can be read and written by the core Upon reset
and whenever the ABORT register is written all the bits in
DSPMASK are cleared to ‘‘0’’
The format of the NMISTAT register is shown in Figure 2-14
15 3 2 1 0
Reserved
ERR UND EXT
FIGURE 2-14 NMISTAT Register Format
The NMISTAT holds the status of the current pending Non-
Maskable Interrupt (NMI) requests
Whenever the core attempts to access the DSPM address
space while the CLSTAT RUN bit is ‘‘1’’ (except for access-
es to the CLSTAT EXT DSPINT NMISTAT DSPMASK
and ABORT registers) NMISTAT ERR is set to ‘‘1’’
Whenever there is an attempt to execute a DBPT instruc-
tion or a reserved DSPM instruction (Section 3 4) the
NMISTAT UND bit is set to ‘‘1’’
When a high to low transition is detected on the NMI input
pin NMISTAT EXT bit is set to ‘‘1’’
When one of the bits in NMISTAT is set to ‘‘1’’ an NMI
request to the core is issued
The NMISTAT register is cleared to 0 upon reset and each
time its contents are read
When one of the bits in NMISTAT is set to 1 an NMI occurs
The NMI handler can read the NMISTAT register to deter-
mine the source of the interrupt Note that since NMIs may
be nested it is possible that a second NMI handler (invoked
while the previous handler has not yet exited) will read and
handle more than one set bit in NMISTAT Since the read
operation clears the register the interrupted handler may
find that no bits are set
2 2 MEMORY ORGANIZATION
The main memory of the NS32FX164 is a uniform linear
address space Memory locations are numbered sequential-
ly starting at zero and ending at 224 b 1 The number speci-
fying a memory location is called an address The contents
of each memory location is a byte consisting of eight bits
Unless otherwise noted diagrams in this document show
data stored in memory with the lowest address on the right
and the highest address on the left Also when data is
shown vertically the lowest address is at the top of a dia-
gram and the highest address at the bottom of the diagram
When bits are numbered in a diagram the least significant
bit is given the number zero and is shown at the right of the
diagram Bits are numbered in increasing significance and
toward the left
70
A
Byte at Address A
Two contiguous bytes are called a word Except where not-
ed the least significant byte of a word is stored at the lower
address and the most significant byte of the word is stored
at the next higher address In memory the address of a
word is the address of its least significant byte and a word
may start at any address
15 8 7
0
Aa1
A
MSB
LSB
Word at Address A
Two contiguous words are called a double-word Except
where noted the least significant word of a double-word is
stored at the lowest address and the most significant word
of the double-word is stored at the address two higher In
memory the address of a double-word is the address of its
least significant byte and a double-word may start at any
address
31 24 23 16 15
87
0
Aa3
Aa2
Aa1
A
MSB
Double Word at Address A
LSB
11
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