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PDF NS486SXF Data sheet ( Hoja de datos )
| Número de pieza | NS486SXF | |
| Descripción | NS486TMSXF Optimized 32-Bit 486-Class Controller with On-Chip Peripherals for Embedded Systems | |
| Fabricantes | National | |
| Logotipo |  |
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ADVANCE INFORMATION
February 1997
NS486TMSXF Optimized 32-Bit 486-Class Controller
with On-Chip Peripherals for Embedded Systems
General Description
The NS486SXF is a highly integrated embedded system
controller incorporating an Intel486TM-class 32-bit proces-
sor all of the necessary System Service Elements and a
set of peripheral I O controllers tailored for embedded con-
trol systems It is ideally suited for a wide variety of applica-
tions running in a segmented protect-mode environment
Key Features
Y 100% compatible with VxWorks VRTX QNX Neu-
trino pSOSaTM and other popular real-time executives
and operating system kernels
Y Intel486 instruction set compatible (protected mode
only) with optimized performance
Y CPU includes a 1 Kbyte Instruction Cache
Y Operation at 25 MHz with 5V supply
Y Low cost 160-pin PQFP package
Y Industry standard interrupt controller timers real time
clock UART with IrDA v1 0 (Infrared Data Association)
port
Y Intel 82365 compatible PCMCIA interface
Y Protected WATCHDOGTM timer
Y Optimized DRAM Controller (supports two banks up to
8 Mbytes each)
Y Up to nine versatile programmable chip selects
Y Glueless interface to ISA peripherals
Y Arbitration support for auxiliary processor
Y Four external DMA channels (max transfer rate of 25
MByte sec 25 MHz) support many transfer modes
Y High performance IEEE 1284 (ECP) Bidirectional
Parallel Port
Y MICROWIRETM Access bus synchronous serial
interfaces
Y LCD Controller for an up to 4 grey scale supertwist
Liquid Crystal Displays up to 480 X 320
Y Reconfigurable I O Up to 29 I O pins can be used as
general purpose bidirectional I O lines
Y Flexible programmable multilevel power saving modes
maximize power savings
NS486SXF Single-Chip Embedded Controller
TRI-STATE is a registered trademark of National Semiconductor Corporation
NS486TM WATCHDOGTM and MICROWIRETM are trademarks of National Semiconductor Corporation
Intel486TM is a trademark of Intel Corporation
QNX is a registered trademark of QNX Software Systems Inc
VRTX is a registered trademark of Microtec Research Inc
VxWorks is a registered trademark of Wind River Systems Inc
pSOSaTM is a trademark of Integrated Systems Inc
PowerPack is a registered trademark of Microtek International
C1996 National Semiconductor Corporation TL EE12514
RRD-B30M27 Printed in U S A
TL EE 12514 – 1
http www national com
1 page  
1 0 System Overview
1 1 NS486SXF SYSTEM OVERVIEW
The NS486SXF is a highly integrated embedded system
controller It includes an Intel486-class 32-bit processor all
resources required for the System Service Elements of a
Real-Time Executive and a generous set of peripherals
This ‘‘system-on-a-chip’’ is ideal for implementing a wide
variety of embedded applications These include (but are
not limited to) fax machines multifunction peripherals (fax
scanners printers) mobile companions (both organizer and
communicator) television set-top boxes and telephones
(mobile and desktop)
The 32-bit processor core executes all of the Intel486 in-
structions with a similar number of clocks per instruction An
on-board 1 kbyte instruction cache provides for efficient ex-
ecution from ROM Intel486 debug features are supported
The processor has been optimized for operating system
kernels such as VRTX VxWorks pSOSa and QNX These
environments only need the ‘486 protected mode operation
(no real mode or virtual 8086 support) flat or linear memory
addressing (no virtual memory paging) and floating point
execution in software only (no co-processor interface)
In fact the NS486SXF includes all of the System Service
Elements required by a typical kernel including an efficient
DRAM controller that supports page-mode DRAMs for data
cache-like performance a six-channel DMA controller with
two channels supporting data transfers from on-chip periph-
erals (the IEEE 1284 ECP or Extended Capabilities Port
and the LCD controller) and four channels supporting exter-
nal devices such as scanners and print engines three timer
channels (including one configured as a protected WATCH-
DOG Timer) two programmable 8259 interrupt controllers
provide 15 on-chip interrupt sources an industry standard
real time clock and calendar (RTC) with battery backup and
support for comprehensive power management schemes
In addition the NS486SXF also incorporates the key I O
peripherals required for implementing a wide variety of em-
bedded applications an IEEE 1284 Bidirectional Parallel
Port that includes both Host and Slave modes an Intel
82365-compatible PCMCIA controller for one card slot an
industry standard high-performance NS16550-compatible
UART with HP-SIR and IrDA v1 0 infrared option an LCD
panel interface with DMA supported refresh for many of the
standard resolutions an 8254 timer and a general purpose
2- or 3-wire synchronous serial interface for easy interface
to low-cost EEPROMs and other serial peripherals System
expansion is supported with nine programmable Chip Select
(CS) signals and a generic ISA-type bus interface for exter-
nal devices and memory
FIGURE 1-1 NS486SXF Internal Resource to Pins Map
5
TL EE 12514 – 2
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5 Page 
2 0 Pin Description Tables (Continued)
TABLE 2-2 DMA Control Pins
Symbol
DRQ 4 DRQ 3
DRQ 2 DRQ 0
DACK 4
DACK 3
DACK 2
DACK 0
TC EOP
Pins
34 32
36 38
35 33
37 39
Type
Function
I DMA ReQuest A DRQn signal requests the internal DMA Controller to transfer data
between the Requesting Device and memory
O DMA ACKnowledge When the CPU has relinquished control of the bus to a requesting DMA
channel the appropriate active-low DACKn signal acknowledges the winning DRQn
40 I O Terminal Count End Of Process This signal may operate either as a terminal count output
or an active-low End of Process input As TC an active-high pulse occurs on this signal when
the terminal count for any DMA channel has been reached As EOP an external device may
terminate the DMA transfer by driving this signal active-low
Symbol
RAS 1 0
CASH 1 0
CASL 1 0
WE
DPH DPL
TABLE 2-3 DRAM Control Pins
Pins
30 31
25 26
28 29
23
1 12
Type
O
O
O
O
IO
Function
Row Address Strobe On the falling edge of these active-low signals Bank 1 and Bank 0
respectively should latch in the row address off of SA 12 1 If only one bank of DRAMs are
supported RAS0 will support that bank and RAS1 will be unused
Column Address Strobe (High Byte) These active-low signals indicate when the column access is
being made to the high byte of DRAM Bank 1 and DRAM Bank 0 respectively If only one bank of
DRAMs are supported CASH0 will support the high byte of that bank and CASH1 will be unused
Column Address Strobe (Low Byte) These active-low signals indicate when the column access is
being made to the low byte of DRAM Bank 1 and DRAM Bank 0 respectively If only one bank of
DRAMs are supported CASL0 will support the low byte of that bank and CASL1 will be unused
Write Enable Active low signal for writing the data into the DRAM bank
DRAM Data Parity DRAM data parity may be enabled or disabled if disabled these two pins will be
unused Otherwise for DRAM writes the NS486SXF’s DRAM Controller will generate odd parity and
drive the odd parity onto these two pins For DRAM reads the NS486SXF’s DRAM Controller will
read the values driven on these two pins and check it for odd parity in association with the
appropriate data byte
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| PDF Descargar | [ Datasheet NS486SXF.PDF ] | |
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