93C56 Datasheet PDF - Microchip Technology
| Part Number | 93C56 | |
| Description | 2K 5.0V Automotive Temperature Microwire Serial EEPROM | |
| Manufacturers | Microchip Technology | |
| Logo |  |
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There is a preview and 93C56 download ( pdf file ) link at the bottom of this page. Total 12 Pages | ||
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M
93C56A/B
2K 5.0V Automotive Temperature Microwire® Serial EEPROM
FEATURES
• Single supply 5.0V operation
• Low power CMOS technology
- 1 mA active current (typical)
- 1 µA standby current (maximum)
• 256 x 8 bit organization (93C56A)
• 128 x 16 bit organization (93C56B)
• Self-timed ERASE and WRITE cycles (including
auto-erase)
• Automatic ERAL before WRAL
• Power on/off data protection circuitry
• Industry standard 3-wire serial interface
• Device status signal during ERASE/WRITE
cycles
• Sequential READ function
• 100,000 E/W cycles guaranteed
• Data retention > 200 years
• 8-pin PDIP and SOIC packages
• Available for the following temperature ranges:
- Automotive (E):
-40°C to +125°C
DESCRIPTION
The Microchip Technology Inc. 93C56A/B is a 2K-bit,
low-voltage serial Electrically Erasable PROM. The
device memory is configured as 256 x 8 bits (93C56A)
or 128 x 16 bits (93C56B). Advanced CMOS technol-
ogy makes this device ideal for low-power, nonvolatile
memory applications. The 93C56A/B is available in
standard 8-pin DIP and surface mount SOIC packages.
This device is only recommeded for 5V automotive
temperature applications. For all commercial and
industrial applications, the 93LC56A/B is recom-
mended.
PACKAGE TYPE
PDIP
CS
VCC
1
CLK 2
DI 3
DO 4
8
7 NC
6 NC
5 VSS
SOIC
CS
CLK
DI
DO
1
2
3
4
8 VCC
7 NC
6 NC
5 VSS
BLOCK DIAGRAM
MEMORY
ARRAY
ADDRESS
DECODER
ADDRESS
COUNTER
DI
CS
CLK
DATA
REGISTER
MEMORY
DECODE
LOGIC
CLOCK
GENERATOR
OUTPUT
BUFFER
DO
VCC
VSS
Microwire is a registered trademark of National Semiconductor.
© 1998 Microchip Technology Inc.
Preliminary
DS21206B-page 1
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3.4 ERASE
The ERASE instruction forces all data bits of the spec-
ified address to the logical “1” state. This cycle begins
on the rising clock edge of the last address bit.
The DO pin indicates the READY/BUSY status of the
device if CS is brought high after a minimum of 250 ns
low (TCSL). DO at logical “0” indicates that program-
ming is still in progress. DO at logical “1” indicates that
the register at the specified address has been erased
and the device is ready for another instruction.
FIGURE 3-2: ERASE TIMING
CS
CLK
93C56A/B
3.5 Erase All (ERAL)
The ERAL instruction will erase the entire memory
array to the logical “1” state. The ERAL cycle is identical
to the ERASE cycle, except for the different opcode.
The ERAL cycle is completely self-timed and com-
mences at the rising clock edge of the last address bit.
Clocking of the CLK pin is not necessary after the
device has entered the ERAL cycle.
The DO pin indicates the READY/BUSY status of the
device, if CS is brought high after a minimum of 250 ns
low (TCSL) and before the entire ERAL cycle is com-
plete.
TCSL
CHECK STATUS
DI
1
1
1
AN AN-1 AN-2 •••
A0
HIGH-Z
DO
TSV
BUSY
TWC
TCZ
READY
HIGH-Z
FIGURE 3-3: ERAL TIMING
CS
TCSL
CHECK STATUS
CLK
DI
1
00
10
X •••
X
HIGH-Z
DO
TSV
BUSY
TEC
TCZ
READY
HIGH-Z
© 1998 Microchip Technology Inc.
Preliminary
DS21206B-page 5
Preview 5 Page |
Part DetailsOn this page, you can learn information such as the schematic, equivalent, pinout, replacement, circuit, and manual for 93C56 electronic component. |
| Information | Total 12 Pages | |
| Link URL | [ Copy URL to Clipboard ] | |
| Download | [ 93C56.PDF Datasheet ] | |
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