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PDF PS12014-A Data sheet ( Hoja de datos )
| Número de pieza | PS12014-A | |
| Descripción | FLAT-BASE TYPE INSULATED TYPE | |
| Fabricantes | Powerex Power | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de PS12014-A (archivo pdf) en la parte inferior de esta página. Total 6 Páginas | ||
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MITMSUITBSIUSBHISSHEI MSIECMOINCDOUNCDTUOCRTO<RAp<pAlipcpaltiicoantioSnpeScpifeicciIfnicteIlnlitgeellnigtePnotwPeorwMerodMuoled>ule>
PS12P0S11420-1A4-A
FLAFTL-BATA-SBEASTEYPTEYPE
INSIUNLSAUTLEADTETDYPTEYPE
PS12014-A
INTEGRATED FUNCTIONS AND FEATURES
• 3-Phase IGBT inverter bridge configured by the latest 3rd.
generation IGBT and diode technologies.
• Circuit for dynamic braking of motor regenerative energy.
• Inverter output current capability Io (Note 1) :
Type Name
PS12014-A
100% load
3.4A (rms)
150% over load
5.1A (rms), 1min
(Note 1) : The inverter output current is assumed to be sinu-
soidal and the peak current value of each of the
above loading cases is defined as : Iop = Io ! √2
INTEGRATED DRIVE, PROTECTION AND SYSTEM CONTROL FUNCTIONS:
• For P-Side IGBTs : Drive circuit, High-speed photo-couplers, Short circuit protection (SC),
Bootstrap circuit supply scheme (Single drive power supply ) and Under-voltage protection (UV).
• For N-Side IGBTs : Drive circuit, Short-circuit protection (SC), Control supply Under voltage and Over voltage protection (OV/UV),
System Over temperature protection (OT), Fault output signaling circuit (Fo), and Current-Limit warning signal out-
put (CL).
• For Brake circuit IGBT : Drive circuit.
• Warning and Fault signaling :
FO1 : Short circuit protection for lower-leg IGBTs and Input interlocking against spurious arm shoot-through.
FO2 : N-side control supply abnormality locking (OV/UV)
FO3 : System over-temperature protection (OT).
CL : Warning for inverter current overload condition
• For system feedback control : Analogue signal feedback reproducing actual inverter output phase current (3φ).
• Input Interface : 5V CMOS/TTL compatible, Schmitt trigger input, and Arm-Shoot-Through interlock protection.
APPLICATION
Acoustic noise-less 0.75kW/AC400V Class 3 Phase inverter and other motor control appli-
cations.
PACKAGE OUTLINES
0.5
1
80.5 ± 1
71.5 ± 0.5
2 ± 0.3
(7.75)
6 ± 0.3
56 ± 0.8
4-φ4
23
2.5
20.4 ± 1
76.5 ± 1
1.2
(10.35)
31 32 33 34
10.16 ± 0.3
50.8 ± 0.8
35 36
4-R4
8.5
13
27 ± 1
Terminals Assignment:
1 CBU+
2 CBU–
3 CBV+
4 CBV–
5 CBW+
6 CBW–
7 GND
8 VDL
9 VDH
10 CL
11 FO1
12 FO2
13 FO3
14 CU
15 CV
16 CW
17 UP
18 VP
19 WP
20 UN
21 VN
22 WN
23 Br
31 P
32 B
33 N
34 U
35 V
36 W
(Fig. 1)
LABEL
Jan. 2000
1 page  
MITSUBISHI SEMICONDUCTOR <Application Specific Intelligent Power Module>
PS12014-A
FLAT-BASE TYPE
INSULATED TYPE
Fig. 4 OUTPUT CURRENT ANALOGUE SIGNALING
LINEARITY
5
VC–
4 min max
VC–(200%)
VDH=15V
VDL=5V
TC=–20~100˚C
3
VC0
2
VC+(200%)
1
Analogue output signal
data hold range
VC+
0
–400 –300 –200 –100 0 100 200 300 400
Real load current peak value.(%)(Ic=Io! 2)
Fig. 5 OUTPUT CURRENT ANALOGUE SIGNALING
“DATA HOLD” DEFINITION
VC
500µs
0V VCH(5µs)
VCH(505µs)
rCH=
VCH(505µs)-VCH(5µs)
VCH(5µs)
Note ; Ringing happens around the point where the signal output
voltage changes state from “analogue” to “data hold” due
to test circuit arrangement and instrumentational trouble.
Therefore, the rate of change is measured at a 5 µs delayed point.
Fig. 6 INPUT INTERLOCK OPERATION TIMING CHART
Input signal VCIN(p) of each phase upper arm 0V
Input signal VCIN(n) of each phase lower arm
Gate signal Vo(p) of each phase upper arm
(ASIPM internal)
0V
0V
Gate signal Vo(n) of each phase upper arm
(ASIPM internal)
0V
Error output FO1 0V
Note : Input interlock protection circuit ; It is operated when the input signals for any upper-arm / lower-arm pair of a phase are simulta-
neously in “LOW” level.
By this interlocking, both upper and lower IGBTs of this mal-triggered phase are cut off, and “FO” signal is outputted. After an “input
interlock” operation the circuit is latched. The “FO” is reset by the high-to-low going edge of either an upper-leg, or a lower-leg input,
whichever comes in later.
Fig. 7 TIMING CHART AND SHORT CIRCUIT PROTECTION OPERATION
Input signal VCIN of each phase
upper arm
0V
Short circuit sensing signal VS
Gate signal Vo of each phase
upper arm(ASIPM internal)
0V
0V
Error output FO1 0V
SC delay time
Note : Short circuit protection operation. The protection operates with “FO” flag and reset on a pulse-by-pulse scheme. The protection by
gate shutdown is given only to the IGBT that senses an overload (excluding the IGBT for the “Brake”).
Jan. 2000
5 Page | ||
| Páginas | Total 6 Páginas | |
| PDF Descargar | [ Datasheet PS12014-A.PDF ] | |
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