N80C31BH Datasheet PDF - Intel Corporation
| Part Number | N80C31BH | |
| Description | CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLER | |
| Manufacturers | Intel Corporation | |
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80C31BH 80C51BH 87C51
MCS 51
CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLER
Automotive
Y Extended Automotive Temperature
Range (b40 C to a125 C Ambient)
Y High Performance CHMOS Process
Y Power Control Modes
Y 4 Kbyte On-Chip ROM EPROM
Y 128 x 8-bit RAM
Y 32 Programmable I O Lines
Y Two 16-Bit Timer Counters
Y 5 Interrupt Sources
Y Quick-Pulse EPROM Programming
Y 2-Level Program Memory Lock EPROM
Y Boolean Processor
Y Programmable Serial Port
Y TTL- and CMOS-Compatible Logic
Levels
Y 64K External Program Memory Space
Y 64K External Data Memory Space
Y IDLE and POWER DOWN Modes
Y ONCE Mode Facilitates System Testing
Y Available in 12 MHz and 16 MHz
Versions
Y Available in PLCC and DIP Packages
(See Packaging Specification Order 231369)
The MCS 51 CHMOS microcontroller products are fabricated on Intel’s reliable CHMOS process and are
functionally compatible with the standard MCS 51 HMOS microcontroller products This technology combines
the high speed and density characteristics of HMOS with the low power attributes of CHMOS This combina-
tion expands the effectiveness of the powerful MCS 51 microcontroller architecture and instruction set
Like the MCS 51 HMOS microcontroller versions the MCS 51 CHMOS microcontroller products have the
following features 4 Kbytes of EPROM ROM (87C51 80C51BH respectively) 128 bytes of RAM 32 I O lines
two 16-bit timer counters a five-source two-level interrupt structure a full duplex serial port and on-chip
oscillator and clock circuitry In addition the MCS 51 CHMOS microcontroller products exhibit low operating
power along with two software selectable modes of reduced activity for further power reduction Idle and
Power Down
The Idle mode freezes the CPU while allowing the RAM timer counters serial port and interrupt system to
continue functioning The Power Down mode saves the RAM contents but freezes the oscillator causing all
other chip functions to be inoperative
The 87C51 is the EPROM version of the 80C51BH It contains 4 Kbytes of on-chip program memory that can
be electrically programmed and can be erased by exposure to ultraviolet light The 87C51 EPROM array uses
a modified Quick-Pulse Programming algorithm by which the entire 4 Kbyte array can be programmed in about
12 seconds
NOTICE
This datasheet contains information on products in full production Specifications within this datasheet
are subject to change without notice Verify with your local Intel sales office that you have the latest
datasheet before finalizing a design
Other brands and names are the property of their respective owners
Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or
copyright for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products Intel retains the right to make
changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata
COPYRIGHT INTEL CORPORATION 1995
January 1995
Order Number 270419-007
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AUTOMOTIVE 80C31BH 80C51BH 87C51
Port 3 also serves the functions of various special
features of the MCS 51 microcontroller family as
listed below
Pin Name
Alternate Function
P3 0
P3 1
P3 2
P3 3
P3 4
P3 5
P3 6
P3 7
RXD
TXD
INT0
INT1
T0
T1
WR
RD
Serial Input Line
Serial Output Line
External Interrupt 0
External Interrupt 1
Timer 0 External Input
Timer 1 External Input
External Data Memory Write Strobe
External Data Memory Read Strobe
Port 3 also receives some control signals for
EPROM programming and program verification
RESET Reset input A logic high on this pin for two
machine cycles while the oscillator is running resets
the device An internal pulldown resistor permits a
power-on reset to be generated using only an exter-
nal capacitor to VCC
ALE PROG (EPROM Only) Address Latch Enable
output signal for latching the low byte of the address
during accesses to external memory This pin is also
the program pulse input (PROG) during EPROM pro-
gramming
In normal operation ALE is emitted at a constant
rate of 1 6 the oscillator frequency and may be
used for external timing or clocking purposes Note
however that one ALE pulse is skipped during each
access to external Data Memory
PSEN Program Store Enable is the Read strobe
to External Program Memory When the
87C51 80C51BH is executing from Internal Program
Memory PSEN is inactive (high) When the device is
executing code from External Program Memory
PSEN is activated twice each machine cycle except
that two PSEN activations are skipped during each
access to External Data Memory
EA VPP External Access enable EA must be
strapped to VSS in order to enable the
87C51 80C51BH to fetch code from External Pro-
gram Memory locations starting at 0000H up to
0FFFFH Note however that if either of the Lock
Bits is programmed the logic level at EA is internally
latched during reset (EPROM only )
EA must be strapped to VCC for internal program
execution
VPP (EPROM Only) This pin also receives the
12 75V programming supply voltage (VPP) during
EPROM programming
270419 – 5
Figure 4 Using the On-Chip Oscillator
270419 – 6
Figure 5 External Clock Drive
XTAL1 Input to the inverting oscillator amplifier and
input to the internal clock generating circuits
XTAL2 Output from the inverting oscillator amplifi-
er
OSCILLATOR CHARACTERISTICS
XTAL1 and XTAL2 are the input and output respec-
tively of an inverting amplifier which can be config-
ured for use as an on-chip oscillator as shown in
Figure 4
To drive the device from an external clock source
XTAL1 should be driven while XTAL2 is left uncon-
nected as shown in Figure 5 There are no require-
ments on the duty cycle of the external clock signal
since the input to the internal clocking circuitry is
through a divide-by-two flip-flop but minimum and
maximum high and low times specified on the Data-
sheet must be observed
IDLE MODE
In Idle Mode the CPU puts itself to sleep while all
the on-chip peripherals remain active The mode is
invoked by software The content of the on-chip
RAM and all the Special Functions Registers remain
unchanged during this mode The Idle Mode can be
terminated by any enabled interrupt or by a hard-
ware reset
It should be noted that when Idle is terminated by a
hardware reset the device normally resumes pro-
gram execution from where it left off up to two ma-
chine cycles before the internal reset algorithm
takes control On-chip hardware inhibits access to
5
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| Information | Total 16 Pages | |
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| Part Number | Description | MFRS |
| N80C31BH | The function is CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLER. Intel Corporation | |
| N80C31BH | The function is CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLER. Intel Corporation | |
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