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PDF S80296SA Data sheet ( Hoja de datos )
| Número de pieza | S80296SA | |
| Descripción | 80296SA COMMERCIAL CHMOS 16-BIT MICROCONTROLLER | |
| Fabricantes | Intel Corporation | |
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PRELIMINARY
80296SA COMMERCIAL
CHMOS 16-BIT MICROCONTROLLER
s 50 MHz Operation†
s 6 Mbytes of Linear Address Space
s 512 Bytes of Register RAM
s 2 Kbytes of Code/Data RAM
s Register-register Architecture
s Footprint and Functionally Compatible
Upgrade for the 8XC196NP and
80C196NU
s Optional Phase-locked Loop (PLL)
Circuitry with 2x or 4x Clock Multiplier
s 32 I/O Port Pins
s 19 Interrupt Sources, 14 with
Programmable Priorities
s 4 External Interrupt Pins and NMI Pin
s 2 Flexible 16-bit Timer/Counters with
Quadrature Counting Capability
s 3 Pulse-width Modulator (PWM)
Outputs with High Drive Capability
s Full-duplex Serial Port with Dedicated
Baud-rate Generator
† 40 MHz standard; 50 MHz is Speed Premium
s Chip-select Unit
— 6 Chip-select Pins
— Dynamic Demultiplexed/Multiplexed
Address/Data Bus for Each
Chip Select
— Programmable Wait States
(0–15) for Each Chip Select
— Programmable Bus Width
(8- or 16-bit) for Each Chip Select
— Programmable Address Range for
Each Chip Select
s Event Processor Array (EPA) with
4 High-speed Capture/Compare
Channels
s Multiply and Accumulate Executes in
80 ns Using the 40-bit Hardware
Accumulator
s 880 ns 32/16 Unsigned Division
s 100-pin QFP Package
s Complete System Development
Support
s High-speed CHMOS Technology
The 80296SA is a member of Intel’s 16-bit MCS® 96 microcontroller family. The 80296SA features 6 Mbytes
of linear address space, a demultiplexed bus, and a chip-select unit. The external bus can dynamically switch
between multiplexed and demultiplexed operation. The device has hardware and instructions to support
various digital signal processing algorithms.
NOTE
This datasheet contains information on new products in production. The specifications
are subject to change without notice. Verify with your local Intel sales office that you have
the latest datasheet before finalizing a design.
COPYRIGHT © INTEL CORPORATION, 1997
January 1997
Order Number: 272748-003
1 page  
80296SA COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
1.0 PRODUCT OVERVIEW
The 80296SA is a member of Intel’s 16-bit MCS® 96 microcontroller family. The 80296SA features 6 Mbytes
of linear address space, a demultiplexed bus, and a chip-select unit. The external bus can dynamically switch
between multiplexed and demultiplexed operation. The device has hardware and instructions to support
various digital signal processing algorithms.
Code/Data
RAM
(2 Kbytes)
Memory Addr Bus (24)
Memory Data Bus (16)
Bus Control Signals
A19:16
A15:0
AD15:0
Bus
Controller
Aligner
Queue
Instruction
Sequencer
Source 1 Addr (24)
Source 1 Data (16)
Source 2 Addr (24)
Source 2 Data (16)
ALU
Register File
(3-port RAM)
Memory
Interface
Unit
Destination Addr (24)
Destination Data (16)
Port 3
Chip-select
Unit
Peripheral
Bus
Interface
Interrupt
Controller
Figure 1. 80296SA Block Diagram
Baud-
SIO rate
Generator
Port 2
PWM
Port 4
EPA
Timer 1
Timer 2
Port 1
A3175-02
PRELIMINARY
1
5 Page 
80296SA COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
Name
BREQ#
CLKOUT
CS5:0#
EPA3:0
EPORT.3:0
Table 4. Signal Descriptions (Continued)
Type
Description
O Bus Request
This active-low output signal is asserted during a hold cycle when the bus controller
has a pending external memory cycle. When the bus-hold protocol is enabled
(WSR.7 is set), the P2.3/BREQ# pin can function only as BREQ#, regardless of the
configuration selected through the port configuration registers (P2_MODE, P2_DIR,
and P2_REG). An attempt to change the pin configuration is ignored until the bus-
hold protocol is disabled (WSR.7 is cleared).
The microcontroller can assert BREQ# at the same time as or after it asserts
HLDA#. Once it is asserted, BREQ# remains asserted until HOLD# is deasserted.
BREQ# shares a package pin with P2.3.
O Clock Output
Output of the internal clock generator. The CLKOUT frequency is ½ the internal
operating frequency (f). CLKOUT has a 50% duty cycle.
CLKOUT shares a package pin with P2.7.
O Chip-select Lines 0–5
The active-low output CSx# is asserted during an external memory cycle when the
address to be accessed is in the range programmed for chip select x or chip select
x+1 if remapping is enabled. If the external memory address is outside the range
assigned to the six chip selects, no chip-select output is asserted and the bus
configuration defaults to the CS5# values.
Immediately following reset, CS0# is automatically assigned to the range FF2000–
FF20FFH.
CS5:0# share package pins with P3.5:0.
I/O Event Processor Array (EPA) Capture/Compare Channels
High-speed input/output signals for the EPA capture/compare channels. For high-
speed PWM applications, the outputs of two EPA channels (either EPA0 and EPA1
or EPA2 and EPA3) can be remapped to produce a PWM waveform on a shared
output pin.
EPA3:0 share package pins with P1.3:0.
I/O Extended Addressing Port
This is a standard 4-bit, bidirectional port.
EPORT.3:0 share package pins with A19:16.
PRELIMINARY
7
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