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PDF 74HC164 Data sheet ( Hoja de datos )
| Número de pieza | 74HC164 | |
| Descripción | 8-bit Parallel-out Shift Register | |
| Fabricantes | Hitachi | |
| Logotipo |  |
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HD74HC164
8-bit Parallel-out Shift Register
Description
This 8-bit shift register has gated serial inputs and clear. Each register bit is a D-type master/slave flip-
flop. Inputs A & B permit complete control over the incoming data. A low at either or both inputs inhibits
entry of new data and resets the first flip-vlop to the low level at the next clock pulse. A high level on the
input enables the other input which will then determine the state of the first flip-flop. Data at the serial
inputs may be changed while the clock is high or low, but only information meeting the setup and hold time
requirements will be entered. Data is serially shifted in and out of the 8-bit register during the positive
going transition of the clock pulse. Clear is independent of the clock and accomplished by a low level at
the clear input.
Features
• High Speed Operation: tpd (Clock to Q) = 14.5 ns typ (CL = 50 pF)
• High Output Current: Fanout of 10 LSTTL Loads
• Wide Operating Voltage: VCC = 2 to 6 V
• Low Input Current: 1 µA max
• Low Quiescent Supply Current: ICC (static) = 4 µA max
Function Table
Inputs
Outputs
Clear
Clock
A
B
QA QB ·········
L X X X L L ·········
H X X QAo QBo ·········
H L X L QAn ·········
H X L L QAn ·········
H H H H QAn ·········
QAo to QHo = Outputs remain unchanged.
QAn to QGn = Data shifted from the previous stage on a positive edge at the clock input.
QH
L
QHo
QGn
QGn
QGn
1 page  
HD74HC164
AC Characteristics (CL = 50 pF, Input tr = tf = 6 ns)
Ta = 25°C
Ta = –40 to
+85°C
Item
Maximum clock
frequency
Symbol
f max
VCC (V)
2.0
4.5
Min Typ Max Min
——5 —
— — 25 —
Max Unit Test Conditions
4 MHz
20
6.0 — — 29 — 24
Propagation delay tPHL
time
2.0 — — 160 — 200 ns Clock to Q
4.5 — 14 32 — 40
6.0 — — 27 — 34
tPLH 2.0 — — 160 — 200 ns
4.5 — 15 32 — 40
6.0 — — 27 — 34
tPHL 2.0 — — 175 — 220 ns Clear to Q
4.5 — 17 35 — 44
6.0 — — 30 — 37
Setup time
tsu 2.0 100 — — 125 — ns A, B to Clock
4.5 20 1 — 25 —
6.0 17 — — 21 —
Hold time
th 2.0 5 — — 5 — ns Clock to A, B
4.5 5 0 — 5 —
6.0 5 — — 5 —
Removal time
t rem
2.0 5 — — 5 — ns Clear to Clock
4.5 5 0 — 5 —
6.0 5 — — 5 —
Pulse width tw 2.0 80 — — 100 — ns Clock
4.5 16 8 — 20 —
6.0 14 — — 17 —
2.0 80 — — 100 — ns Clear
4.5 16 5 — 20 —
6.0 14 — — 17 —
Output rise/fall
time
t TLH
t THL
2.0 — — 75 — 95 ns
4.5 — 5 15 — 19
6.0 — — 13 — 16
Input capacitance Cin — — 5 10 — 10 pF
5
5 Page | ||
| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet 74HC164.PDF ] | |
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