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PDF MTV212MN64 Data sheet ( Hoja de datos )
| Número de pieza | MTV212MN64 | |
| Descripción | 8051 Embedded Monitor Controller Flash Type with ISP | |
| Fabricantes | ETC | |
| Logotipo |  |
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MYSON
TECHNOLOGY
MTV212M64i
(Rev 0.9)
8051 Embedded Monitor Controller
Flash Type with ISP
FEATURES
• 8051 core, 12MHz operating frequency.
• 1024-byte RAM; 64K-byte program Flash-ROM support In System Programming(ISP).
• Maximum 14 channels of 5V open-drain PWM DAC.
• Maximum 32 bi-directional I/O pins.
• SYNC processor for composite separation/insertion, H/V polarity/frequency check, polarity adjustment
and programmable clamp pulse output.
• Built-in self-test pattern generator with four free-running timings.
• Built-in low power reset circuit.
• Compliant with VESA DDC1/2B/2Bi/2B+ standard.
• Dual slave IIC addresses.
• Single master IIC interface for internal device communication.
• 4-channel 6-bit ADC.
• Watchdog timer with programmable intervals.
• 40-pin DIP, 42-pin SDIP or 44-pin PLCC package.
GENERAL DESCRIPTIONS
The MTV212M64i micro-controller is an 8051 CPU core embedded device especially tailored to Monitor
applications. It includes an 8051 CPU core, 1024-byte SRAM, SYNC processor, 14 built-in PWM DACs,
VESA DDC interface, 4-channel A/D converter and a 64K-byte internal program Flash-ROM.
BLOCK DIAGRAM
P1.0-7
P2.0-2,P2.4-7
P3.2-0
P3.4-5
P0.0-
7
RD
WR
ALE
INT1
RST 8051
X1
X2
P0.0-
7
RD
WR
ALE
INT1
XFR
AD0-2 ADC
H/VSYNC
CONTROL
STOUT
HBLANK
VBLANK
HSYNC
VSYNC
HCLAMP
HALFV
HALFH
14 CHANNEL
PWM DAC
DDC & IIC
INTERFACE
ISCL
ISDA
HSCL
HSDA
This datasheet contains new product information. Myson Technology reserves the rights to modify the product specification without
notice. No liability is assumed as a result of the use of this product. No rights under any patent accompany the sale of the product.
Revision 0.9
-1-
2000/11/16
1 page  
MYSON
TECHNOLOGY
MTV212M64i
(Rev 0.9)
FUNCTIONAL DESCRIPTIONS
1. 8051 CPU Core
MTV212M64i includes all 8051 functions with the following exceptions:
1.1 The external RAM access is restricted to XFRs/AUXRAM within the MTV212M64i.
1.2 Port0, port3.3, port3.6 and port3.7 are not general-purpose I/O ports. They are dedicated to monitor
special application.
1.3 INT1 input pin is not provided, it is connected to special interrupt sources.
1.4 Port2 is shared by special function pins.
In addition, there are 2 timers, 5 interrupt sources and a serial interface compatible with the standard 8051.
Note: All registers listed in this document reside in external RAM area (XFR). For internal RAM memory map,
please refer to 8051 spec.
2. Memory Allocation
2.1 Internal Special Function Registers (SFR)
The SFR is a group of registers that are the same as standard 8051.
2.2 Internal RAM
There are total 256 bytes internal RAM in MTV212M64i, same as standard 8052.
2.3 External Special Function Registers (XFR)
The XFR is a group of registers allocated in the 8051 external RAM area 00h - 7Fh. Most of the registers are
used for monitor control or PWM DAC. Program can initialize Ri value and use "MOVX" instruction to access
these registers.
2.4 Auxiliary RAM (AUXRAM)
There are a total of 768 bytes auxiliary RAM allocated in the 8051 external RAM area 80h - FFh. The
AUXRAM is divided into six banks, selected by XBANK register. Program can initialize Ri value and use
"MOVX" instruction to access the AUXRAM.
FFh Internal RAM
SFR
Accessible by
indirect
addressing only
(Using
MOV A,@Ri
instruction)
80h
7Fh Internal RAM
Accessible by
direct addressing
Accessible by
direct and indirect
addressing
00h
Revision 0.9
FFh AUXRAM
Accessible by
indirect external
RAM addressing
(XBANK=0)(Using
MOVX A,@Ri
instruction)
80h
7Fh XFR
Accessible by
indirect external
RAM addressing
(Using
MOVX A,@Ri
instruction
00h
-5-
… ..
XBANK=
2,3,4,5
AUXRAM
Accessible by
indirect external
RAM addressing
(XBANK=5)(Using
MOVX A,@Ri
instruction)
2000/11/17
5 Page 
MYSON
TECHNOLOGY
MTV212M64i
(Rev 0.9)
6.4 H/V Polarity Detect
The polarity functions detect the input HSYNC/VSYNC high and low pulse duty cycle. If the high pulse
duration is longer than that of the low pulse, the negative polarity is asserted; otherwise, positive polarity is
asserted. The HPLchg interrupt is set when the Hpol value changes. The VPLchg interrupt is set when the
Vpol value changes.
6.5 Output HBLANK/VBLANK Control and Polarity Adjust
The HBLANK is the mux output of HSYNC, composite Hpulse and self-test horizontal pattern. The VBLANK
is the mux output of VSYNC, CVSYNC and self-test vertical pattern. The mux selection and output polarity
are S/W controllable. The VBLANK output is cut off when VSYNC frequency is over 200Hz. The
HBLANK/VBLANK shares the output pin with P4.1/ P4.0.
6.6 Self-Test Pattern Generator
For testing purposes, this generator can generate 4 display patterns, which are positive cross-hatch,
negative cross-hatch, full white, and full black (showed as following figure). The HBLANK output frequency of
the pattern can be chosen to 95.2KHz, 63.5KHz, 47.6KHz and 31.75KHz. The VBLANK output frequency of
the pattern is 72Hz or 60Hz. It is originally designed to support monitor manufacturers to do burn-in test, or
offer end-users a reference to check the monitor. The output STOUT of the generator shares the output pin
with P4.2.
Display Region
Positive cross-hatch
Negative cross-hatch
Full white
Revision 0.9
Full black
- 11 -
2000/11/17
11 Page | ||
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