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PDF ZL30106 Data sheet ( Hoja de datos )
| Número de pieza | ZL30106 | |
| Descripción | SONET/SDH/PDH Network Interface DPLL | |
| Fabricantes | Zarlink | |
| Logotipo |  |
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ZL30106
SONET/SDH/PDH
Network Interface DPLL
Data Sheet
Features
• Synchronizes to clock-and-sync-pair to maintain
minimal phase skew between inputs and outputs
• Supports output wander and jitter generation
specifications for SONET/SDH and PDH
interfaces
• Accepts three input references and synchronizes
to any combination of 2 kHz, 8 kHz, 1.544 MHz,
2.048 MHz, 8.192 MHz, 16.384 MHz or 19.44 MHz
inputs
• Provides a range of clock outputs:
- 2.048 MHz (E1), 16.384 MHz and either
4.096 MHz and 8.192 MHz or 32.768 MHz and
65.536 MHz
- 19.44 MHz (SONET/SDH)
- 1.544 MHz (DS1) and 3.088 MHz
- a choice of 6.312 MHz (DS2), 8.448 MHz (E2),
44.736 MHz (DS3) or 34.368 MHz (E3)
• Provides 5 styles of 8 kHz framing pulses and a
2 kHz multi-frame pulse
• Provides automatic entry into Holdover and return
from Holdover
• Manual and automatic hitless reference switching
• Provides lock, holdover and accurate reference
fail indication
October 2004
Ordering Information
ZL30106QDG 64 pin TQFP
-40°C to +85°C
• Selectable loop filter bandwidth of 29 Hz or
922 Hz
• Less than 24 psrms intrinsic jitter on the
19.44 MHz output clock, compliant with GR-253-
CORE OC-3 and G.813 STM-1 specifications
• Less than 0.6 nspp intrinsic jitter on all PDH output
clocks and frame pulses
• Selectable external master clock source: clock
oscillator or crystal
• Simple hardware control interface
Applications
• Line card synchronization for SONET/SDH and
PDH systems
• Wireless base-station Network Interface Card
• AdvancedTCA™ and H.110 line cards
OSCi OSCo TIE_CLR
BW_SEL LOCK
OUT_SEL2
REF0
REF_SYNC0
REF1
REF_SYNC1
REF2
REF_FAIL0
REF_FAIL1
REF_FAIL2
APP_SEL1:0
REF_SEL1:0
RST
Master Clock
MUX
TIE
Corrector
Circuit
Virtual
Reference
DPLL
E1
Synthesizer
Reference
Monitor
TIE
Corrector
Enable
State Machine
Mode
Control
Frequency
Select
MUX
DS1
Synthesizer
SDH
Synthesizer
Programmable
Synthesizer
IEEE
1149.1a
C2o
C4/C65o
C8/C32o
C16o
F4/F65o
F8/F32o
F16o
C1.5o
C3o
C19o
F2ko
C6/8.4/34/44o
OUT_SEL1:0
TRST
MODE_SEL1:0 HMS
HOLDOVER
TCK TDI TMS TDO
Figure 1 - Functional Block Diagram
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2004, Zarlink Semiconductor Inc. All Rights Reserved.
1 page  
ZL30106
Data Sheet
List of Figures
Figure 1 - Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 2 - Pin Connections (64 pin TQFP, please see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 3 - Reference Monitor Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 4 - Behaviour of the Dis/Re-qualify Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 5 - Out-of-Range Thresholds for APP_SEL1:0=00. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 6 - Out-of-Range Thresholds for APP_SEL1:0=01. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 7 - Out-of-Range Thresholds for APP_SEL1:0=10 or APP_SEL1:0=11. . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 8 - REF_SYNC Monitor Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 9 - Timing Diagram of Hitless Reference Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 10 - Timing Diagram of Hitless Mode Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 11 - DPLL Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 12 - Mode Switching in Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 13 - Reference Switching in Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 14 - Reference Selection in Automatic Mode (MODE_SEL=11). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 15 - Mode Switching in Automatic Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 16 - Automatic Reference Switching - Coarse Reference Failure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 17 - Automatic Reference Switching - Out-of-Range Reference Failure . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 18 - Examples of REF & REF_SYNC to Output Alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 19 - Recommended Power Supply Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 20 - Clock Oscillator Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 21 - Crystal Oscillator Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 22 - Power-Up Reset Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 23 - Timing Parameter Measurement Voltage Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 24 - REF0/1/2 Input Timing and Input to Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 25 - REF_SYNC0/1 Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 26 - E1 Output Timing Referenced to F8/F32o. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 27 - DS1 Output Timing Referenced to F8/F32o . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 28 - SDH Output Timing Referenced to F8/F32o . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 29 - DS3, E3, E2 and DS2 Output Timing Referenced to F8/F32o . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
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Zarlink Semiconductor Inc.
5 Page 
ZL30106
Data Sheet
Pin #
55
56
57
58
59
60
61
62
63
64
Name
Description
REF0
Reference (Input). This is one of three (REF0, REF1 and REF2) input reference sources
used for synchronization. One of seven possible frequencies may be used: 2 kHz, 8 kHz,
1.544 MHz, 2.048 MHz, 8.192 MHz, 16.384 MHz or 19.44 MHz. This pin is internally
pulled down to GND.
REF_SYNC0
REF Synchronization Frame Pulse 0 (Input). This is the 2 kHz or 8 kHz (multi) frame
pulse synchronization input associated with the REF0 reference. While the PLL is locked
to the REF0 input reference the output (multi) frame pulses are synchronized to this
input. This pin is internally pulled down to GND.
REF1
Reference (Input). See REF0 pin description.
REF_SYNC1
REF Synchronization Frame Pulse 1 (Input). This is the 2 kHz or 8 kHz (multi) frame
pulse synchronization input associated with the REF1 reference. While the PLL is locked
to the REF1 input reference the output (multi) frame pulses are synchronized to this
input. This pin is internally pulled down to GND.
REF2
Reference (Input). See REF0 pin description.
APP_SEL0 Application Selection (Input). See APP_SEL1 pin description.
VDD Positive Supply Voltage. +3.3 VDC nominal
NC No internal bonding Connection. Leave unconnected.
TIE_CLR TIE Circuit Reset (Input). A logic low at this input resets the Time Interval Error (TIE)
correction circuit resulting in a realignment of input phase with output phase.
BW_SEL Filter Bandwidth Selection (Input). This pin selects the bandwidth of the DPLL loop
filter, see Table 2 on page 20.
11
Zarlink Semiconductor Inc.
11 Page | ||
| Páginas | Total 48 Páginas | |
| PDF Descargar | [ Datasheet ZL30106.PDF ] | |
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