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PDF W65C22S Data sheet ( Hoja de datos )
| Número de pieza | W65C22S | |
| Descripción | VIA | |
| Fabricantes | Western Design | |
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The Western Design Center, Inc.
May 2003
1
W65C22S Data Sheet
W65C22S
Versatile Interface Adapter (VIA)
DATA SHEET
The Western Design Center, Inc., 2003. All rights reserved
WDC
1 page  
The Western Design Center, Inc.
W65C22S Data Sheet
Table of Figures
FIGURE 1-1 READ HANDSHAKE OPERATION (PA ONLY) ......................................................................................... 11
FIGURE 1-2 WRITE HANDSHAKE (PA AND PB)............................................................................................................ 12
FIGURE 1-3 ONE-SHOT MODE (TIMER 1 AND TIMER 2) ............................................................................................... 17
FIGURE 1-4 FREE-RUN MODE (TIMER 1) ....................................................................................................................... 18
FIGURE1-5 PULSE COUNTING MODE (TIMER 2).......................................................................................................... 20
FIGURE1-6 SHIFT IN - COUNTER T2 CONTROL............................................................................................................ 22
FIGURE-1-7 SHIFT IN - PHI2 CLOCK CONTROL............................................................................................................ 22
FIGURE 1-8 SHIFT IN - EXTERNAL CB1 CLOCK CONTROL TIMING........................................................................ 23
FIGURE 1-9 SHIFT OUT - FREE RUNNING T2 RATE TIMING ..................................................................................... 23
FIGURE 1-10 SHIFT OUT - T2 CONTROL TIMING ......................................................................................................... 24
FIGURE 1-11 SHIFT OUT - PHI2 CONTROL TIMING ..................................................................................................... 24
FIGURE 1-12 SHIFT OUT - EXTERNAL CB1 CLOCK CONTROL TIMING.................................................................. 25
FIGURE 2-1 PIN PLCC PINOUT ......................................................................................................................................... 28
FIGURE 2-2 W65C22S 40 PIN PDIP PINOUT .................................................................................................................... 29
FIGURE 2-3 W65C22S 44 PIN QFP PINOUT ..................................................................................................................... 30
FIGURE 2-4 PORT A BUFFER (PA0-PA7, CA2)................................................................................................................ 33
FIGURE 2-5 PORT B BUFFER (PB0-PB7, CB1, AND CB2).............................................................................................. 33
FIGURE 3-1 IDD VS VDD.................................................................................................................................................... 36
FIGURE 3-2 F MAX VS VDD .............................................................................................................................................. 36
FIGURE 3-3 READ TIMING................................................................................................................................................. 39
FIGURE 4-1 IRQB DIFFERENCE........................................................................................................................................ 44
FIGURE 4-2 HIGH RESISTANCE BUS HOLDING DEVICE............................................................................................ 45
The Western Design Center, Inc.
W65C22S Datasheet
5
5 Page 
The Western Design Center, Inc.
W65C22S Data Sheet
1.3. Read Handshake Control.
Read Handshaking provides effective control of data transfers from a peripheral device to the microprocessor. To
accomplish the Read Handshake, the peripheral device generates a Data Ready signal to the W65C22S that
indicates valid data is present on PA or PB. In most cases, this Data Ready signal will interrupt the
microprocessor, which will then read the data and generate a Data Taken signal. Once the peripheral senses the
Data Taken signal, new data will be placed on the bus. This process continues until the data transfer is complete.
Automatic Read Handshaking applies to PA only. The Data Ready signal is transmitted by the peripheral device
over the CA1 interrupt line, while the Data Taken signal is generated and transmitted to the peripheral device
over the CA2 line. When the Data Ready signal is received, it sets an internal flag in the Interrupt Flag Register
(IFR). This flag may interrupt the microprocessor or it may be polled under program control. As an option, the
Data Taken signal may be either a pulse or a level. In either case, it is set to a Logic 0 by the microprocessor and is
set by the next Data Ready signal, see Figure 1-1.
Figure 1-1 Read Handshake Operation (PA Only)
The Western Design Center, Inc.
W65C22S Datasheet
11
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