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PDF M80C85 Data sheet ( Hoja de datos )
| Número de pieza | M80C85 | |
| Descripción | 8-Bit CMOS MICROPROCESSOR | |
| Fabricantes | OKI | |
| Logotipo |  |
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E2O0009-27-X2
¡ Semiconductor¡ Semiconductor
MTShMis8v0eCrs8i5oAn:HJRaSn./G19S9/8JS
Previous version: Aug. 1996
MSM80C85AHRS/GS/JS
8-Bit CMOS MICROPROCESSOR
GENRAL DESCRIPTION
The MSM80C85AH is a complete 8-bit parallel; central processor implemented in silicon gate
C-MOS technology and compatible with MSM80C85A.
It is designed with higher processing speed (max.5 MHz) and lower power consumption
compared with MSM80C85A and power down mode is provided, thereby offering a high level
of system integration.
The MSM80C85AH uses a multiplexed address/data bus. The address is split between the 8-
bit address bus and the 8-bit data bus. The on-chip address latch : of a MSM81C55-5 memory
product allows a direct interface with the MSM80C85AH.
FEATURES
• Power down mode (HALT-HOLD)
• Low Power Dissipation: 50mW(Typ)
• Single + 3 to + 6 V Power Supply
• –40 to + 85°C, Operating Temperature
• Compatible with MSM80C85A
• 0.8 ms instruction Cycle (VCC = 5V)
• On-Chip Clock Generator (with External Crystal)
• On-Chip System Controller; Advanced Cycle Status Information Available for Large System
Control
• Bug operation in MSM80C85AH is fixed
• Four Vectored interrupt (One is non-maskable) Plus the 8080A-compatible interrupt.
• Serial, In/Serial Out Port
• Decimal, Binary and Double Precision Arithmetic
• Addressing Capability to 64K Bytes of Memory
• TTL Compatible
• 40-pin Plastic DIP(DIP40-P-600-2.54): (Product name: MSM80C85AHRS)
• 44-pin Plastic QFJ(QFJ44-P-S650-1.27): (Product name: MSM80C85AHJS)
• 44-pin Plastic QFP(QFP44-P-910-0.80-2K): (Product name: MSM80C85AHGS-2K)
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1 page  
¡ Semiconductor
MSM80C85AHRS/GS/JS
Symbol
RESET IN
(Input)
RESET OUT
(Output)
X1, X2
(Input)
CLK
(Output)
SID
(Input)
SOD
(Output)
VCC
GND
Function
Sets the Program Counter to zero and resets the Interrupt Enable and HLDA flip-flops and release
power down mode. The data and address buses and the control lines are 3-stated during RESET and
because of the asynchronous nature of RESET IN, the processor's internal registers and flags may be
altered by RESET with unpredictable results. RESET IN is a Schmitt-triggered input, allowing
connection to an R-C network for power-on RESET delay. The cpu is held in the reset condition as
long as RESET IN is applied.
Indicated cpu is being reset. Can be used as a system reset. The signal is synchronized to
the processor clock and lasts an integral number of clock periods.
X1 and X2 are connected to a crystal to drive the internal clock generator. X1 can also be an external
clock input from a logic gate. The input frequency is divided by 2 to give the processor's internal
operating frequency.
Clock Output for use as a system clock. The period of CLK is twice the X1, X2 input period.
Serial input data line. The data on this line is loaded into accumulator bit 7 whenever a RIM instruction
is executed.
Serial output data line. The output SOD is set or reset as specified by the SIM instruction.
+ 5 Volt supply
Ground Reference.
Name
TRAP
RST 7.5
RST 6.5
RST 5.5
INTR
Table 1 Interrupt Priority, Restart Address, and Sensitivity
Priority
1
2
3
4
5
Address Branched To (1)
When Interrupt Occurs
24H
3CH
34H
2CH
(2)
Type Trigger
Rising edge and high level unit sampled.
Rising edge (latched).
High level unitl sampled.
High level until sampled.
High level until sampled.
Notes: (1) The processor pushes the PC on the stack before branching to the indicated
address.
(2) The address branched to depends on the instruction provided to the cpu
when the interrupt is acknowledged.
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5 Page 
¡ Semiconductor
MSM80C85AHRS/GS/JS
POWER DOWN Mode
The MSM80C85AH is compatible with the MSM80C85A in function and POWER DOWN mode.
This reduces power consumption further.
There are two methods available for starting this POWER DOWN mode. One is through
software control by using the HALT command and the other is under hardware control by using
the pin HOLD. This mode is released by the HOLD, RESET, and interrupt pins (TRAP, RST7.5,
RST6.5 RST5.5, or INTR). (See Table 4.)
Since the sequence of HALT, HOLD, RESET, and INTERRUPT is compatible with MSM80C85A,
every the POWER DOWN mode can be used with no special attention.
Table 4 POWER DOWN Mode Releasing Method
Start by means of Halt command
Start by means of HOLD pin
Released by using pins RESET and INTERRUPT (not by pin HOLD)
Released by using RESET and HOLD pins (not by interrupt pins)
(1) Start by means of HALT command (See Figures 6 and 7.)
The POWER DOWN mode can be started by executing the HALT command.
At this time, the system is put into the HOLD status and therefore the POWER DOWN mode
cannot be released even when the HOLD is released later.
In this case, the POWER DOWN mode can be released by means of the RESET or interrupt.
(2) Start by means of HOLD pin (See Figure 8.)
During the execution of commands other than the HALT, the POWER DOWN mode is started
when the system is put into HOLD status by means of the HOLD pin.
Since no interrupt works during the execution of the HOLD, the POWER DOWN mode cannot
be released by means of interrupt pins. In this case, the POWER DOWN mode can be released
either by means of the RESET pin or by releasing the HOLD status by means of HOLD pin.
11/29
11 Page | ||
| Páginas | Total 29 Páginas | |
| PDF Descargar | [ Datasheet M80C85.PDF ] | |
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