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PDF ST10F167 Data sheet ( Hoja de datos )
| Número de pieza | ST10F167 | |
| Descripción | 16-BIT MCU WITH 128K BYTE FLASH MEMORY | |
| Fabricantes | ST Microelectronics | |
| Logotipo |  |
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ST10F167
16-BIT MCU WITH 128K BYTE FLASH MEMORY
PRELIMINARY DATASHEET
s High Performance 16-bit CPU with 4-Stage
Pipeline
s 100 ns Instruction Cycle Time at 20MHz CPU
Clock
s 500 ns Multiplication (16 × 16 bit), 1 µs Division
(32 / 16 bit)
s Enhanced Boolean Bit Manipulation Facilities
s Additional Instructions to Support HLL and
Operating Systems
s Register-Based Design with Multiple Variable
Register Banks
s Single-Cycle Context Switching Support
s Clock Generation via on-chip PLL or via direct
clock input
s Up to 16 MBytes Linear Address Space for
Code and Data
s 2K Bytes On-Chip Internal RAM (IRAM)
s 2K Bytes On-Chip Extension RAM (XRAM)
s 128K Bytes On-Chip FLASH memory
s FLASH Memory organized into 4 banks
independently erasable
s Programmable External Bus Characteristics for
Different Address Ranges
s 8-Bit or 16-Bit External Data Bus
s Multiplexed or Demultiplexed External Address/
Data Buses
s Five Programmable Chip-Select Signals
s Hold- and Hold-Acknowledge Bus Arbitration
Support
s 1024 Bytes On-Chip Special Function Register
Area
s Idle and Power Down Modes
s 8-Channel Interrupt-Driven Single-Cycle Data
Transfer Facilities via Peripheral Event
Controller (PEC)
s 16-Priority-Level Interrupt System with 56
Sources, Sample-Rate down to 50 ns
s 16-Channel 10-bit A/D Converter with 9.7µs
Conversion Time
s Two 16-Channel Capture/Compare Units
Internal
FLASH
Memory
32
XRA M
16
16
CAN
C PU-C ore
PE C
Interrupt Controller
16
16
Internal
R AM
W atchdog
OSC .
16
16
16
8
Port 6
8
Port 5
16
BR G
BRG
Port 3
15
Port 7
8
16
Port 8
8
s 4-Channel PWM Unit
s Two Multi-Functional General Purpose Timer
Units with 5 Timers
s Two Serial Channels (Synchronous/
Asynchronous and High-Speed-Synchronous)
s On-Chip CAN 2.0B Interface with 15 Message
Objects (Full-CAN/Basic-CAN)
s Programmable Watchdog Timer
s Up to 111 General Purpose I/O Lines, partly
with Selectable Input Thresholds and
Hysteresis
s Supported by development tools: C-Compilers,
Macro-Assembler Packages, Emulators,
Evaluation
Boards,
HLL-Debuggers,
Simulators, Logic Analyzer Disassemblers,
Programming Boards
s On-Chip Bootstrap Loader
s 144-Pin PQFP Package
May 1997
This is preliminary information on a new product indevelopment or undergoing evaluation. Details are subject to change without notice.
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1
1 page  
2 PIN DATA
P6.0/CS0
P6.1/CS1
P6.2/CS2
P6.3/CS3
P6.4/CS4
P6.5/HOLD
P6.6/HLDA
P6.7/BREQ
P8.0/CC16IO
P8.1/CC17IO
P8.2/CC18IO
P8.3/CC19IO
P8.4/CC20IO
P8.5/CC21IO
P8.6/CC22IO
P8.7/CC23IO
VDD
VSS
P7.0/POU T0
P7.1/POU T1
P7.2/POU T2
P7.3/POU T3
P7.4/CC28I0
P7.5/CC29I0
P7.6/CC30I0
P7.7/CC31I0
P5.0AN0
P5.1/AN 1
P5.2/AN 2
P5.3/AN 3
P5.4/AN 4
P5.5/AN 5
P5.6/AN 6
P5.7/AN 7
P5.8/AN 8
P5.9/AN 9
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
ST10F167
ST10F167
108 POH.0/AD8
107 POL.7/AD7
106 POL.6/AD6
105 POL.5/AD5
104 POL.4/AD4
103 POL.3/AD3
102 POL.2AD2
101 POL.A/AD1
100 POL.0/AD0
99 EA
98 ALE
97 READY
96 WR/WRL
95 RD
94 VSS
93 VDD
92 P4.7/A23
91 P4.6/A22/CAN_TXD
90 P4.5/A21/CAN_RXD
89 P4.4/A20
88 P4.3/A19
87 P4.2/A18
86 P4.1/A17
85 P4.0/A16
84 VPP
83 VSS
82 VDD
81 P3.15/CLKOUT
80 P3.13/SCLK
79 P3.12/BHE/WRH
78 P3.11/RXD0
77 P3.10/TXD0
76 P3.9/MTSR
75 P3.8/MRST
74 P3.7/T2IN
73 P3.6/T3IN
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3
5 Page 
ST10F167
Table 2.1
Symbol
VDD
VSS
Pin Definitions and Functions (cont’d)
Pin
Number
46, 82,
136
Input (I)
Output
(O)
-
17, 56,
72, 93,
109,126,
144
45, 83,
139
18, 55,
71, 94,
110,127,
143
-
-
-
Function
Digital Supply Voltage for internal circuitry:
+ 5 V during normal operation and idle mode.
≥ 2.5 V during power down mode
Digital Supply Voltage for port drivers:
+ 5 V during normal operation and idle mode
Digital Ground for internal circuitry.
Digital Ground for port drivers.
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