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PDF V53C1664H Data sheet ( Hoja de datos )

Número de pieza V53C1664H
Descripción High Performance Fast Page Mode Dual Cas CMOS Dynamic RAM
Fabricantes Mosel-Vitelic 
Logotipo Mosel-Vitelic Logotipo



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No Preview Available ! V53C1664H Hoja de datos, Descripción, Manual

MOSEL VITELIC
V53C1664H
HIGH PERFORMANCE
64K X 16 BIT FAST PAGE MODE
DUAL CAS CMOS DYNAMIC RAM
HIGH PERFORMANCE
Max. RAS Access Time, (tRAC)
Max. Column Address Access Time, (tCAA)
Min. Fast Page Mode Cycle Time, (tPC)
Min. Read/Write Cycle Time, (tRC)
30
30 ns
16 ns
19 ns
65 ns
35
35 ns
18 ns
21 ns
70 ns
40
40 ns
20 ns
23 ns
75 ns
45
45 ns
22 ns
25 ns
80 ns
50
50 ns
24 ns
28 ns
90 ns
Features
s 64K x 16-bit organization
s Fast Page Mode for a sustained data rate
of 53 MHz
s RAS access time: 30, 35, 40, 45, 50ns
s Dual CAS Inputs
s Low Power Dissipation
s Read-Modify-Write, RAS-Only Refresh,
CAS-Before-RAS Refresh
s Refresh Interval: 256 cycles/4 ms
s Available in 40-pin 400 mil SOJ and 40/44L-pin
400 mil TSOP-II packages
s Single +5V±10% Power Supply
s TTL Interface
Description
The V53C1664H is a 65,536 x 16 bit high
performance CMOS dynamic random access
memory. The V53C1664H offers Fast Page mode
with dual CAS inputs. The V53C1664H has
symmetric address, 8-bit row and 8-bit column.
All inputs are TTL compatible. Fast Page Mode
operation allows random access up to 256 x 16
bits, within a page, with cycle times as short as
19ns.
The V53C1664H is ideally suited for a wide
variety of high performance computer systems and
peripheral applications.
Device Usage Chart
Operating
Temperature
Range
0°C to 70°C
Package Outline
Access Time (ns)
K T 30 35 40 45 50
• • •••••
Power
Std.
Temperature
Mark
Blank
V53C1664H Rev. 1.0 February 1998
1

1 page




V53C1664H pdf
MOSEL VITELIC
V53C1664H
AC Characteristics
TA = 0°C to 70°C, VCC = 5 V ±10%, VSS = 0V unless otherwise noted
AC Test conditions, input pulse levels 0 to 3V
Symbol Parameter
tRAS
tRC
tRP
tCSH
tCAS
tRCD
tRCS
tASR
tRAH
tASC
tCAH
tRSH (R)
tCRP
tRCH
RAS Pulse Width
Read or Write Cycle Time
RAS Precharge Time
CAS Hold Time
CAS Pulse Width
RAS to CAS Delay
Read Command Setup Time
Row Address Setup Time
Row Address Hold Time
Column Address Setup Time
Column Address Hold Time
RAS Hold Time (Read Cycle)
CAS to RAS Precharge Time
Read Command Hold Time
Referenced to CAS
tRRH
Read Command Hold Time
Referenced to RAS
tROH
RAS Hold Time
Referenced to OE
tOAC
tCAC
tRAC
tCAA
Access Time from OE
Access Time from CAS
Access Time from RAS
Access Time from Column
Address
tLZ OE or CAS to Low-Z Output
tHZ OE or CAS to High-Z Output
tAR Column Address Hold Time from
RAS
tRAD RAS to Column Address
Delay Time
tRSH (W) RAS or CAS Hold Time in
Write Cycle
tCWL
Write Command to CAS
Lead Time
tWCS
tWCH
Write Command Setup Time
Write Command Hold Time
30 35 40 45 50
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit Notes
30 75K 35 75K 40 75K 45 75K 50 75K ns
65 70 75 80 90 ns
25 25 25 25 30 ns
30 35 40 45 50 ns
5 6 7 8 9 ns
15 20 16 24 17 28 18 32 19 36 ns
0 0 0 0 0 ns 4
0 0 0 0 0 ns
5 6 7 8 9 ns
0 0 0 0 0 ns
5 5 5 6 7 ns
10 10 10 10 10 ns
5 5 5 5 5 ns
0 0 0 0 0 ns 5
0 0 0 0 0 ns 5
6 7 8 9 10 ns
10 11 12 13 14 ns 12
10 11 12 13 14 ns 6,7,14
30 35 40 45 50 ns 6, 8, 9
16 18 20 22 24 ns 6,7,10
0 0 0 0 0 ns 16
0 5 0 6 0 6 0 7 0 8 ns 16
26 28 30 35 40 ns
10 14 11 17 12 20 13 23 14 26 ns 11
10 10 10 10 10 ns
10 11 12 13 14 ns
0 0 0 0 0 ns 12, 13
5 5 5 6 7 ns
V53C1664H Rev. 1.0 February 1998
5

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V53C1664H arduino
MOSEL VITELIC
V53C1664H
Waveforms of Fast Page Mode Read Cycle
V IH
RAS
V IL
V IH
UCAS, LCAS
V IL
ADDRESS V IH
V IL
V IH
WE
V IL
V IH
OE
V IL
V OH
I/O
V OL
t RASP
t AR
t RP
t RCD
t CRP
t PC
t CP
t CAS
t CAS
t RSH (R)
t CAS
tCRP
t ASR
t RAH
t ASC
ROW
ADDRESS
t RCS
t CSH
COLUMN
ADDRESS
t RCH
t CAH
COLUMN
ADDRESS
t ASC
t CAH
t RCS
t CAR
COLUMN
ADDRESS
t RCS
t CAH
t RCH
t CAA
t OAC
t CAP
t OAC
t CAA
t OAC
t RRH
t RAC
t CAC
t LZ
t HZ
t CAC
t HZ
t LZ
VALID
DATA OUT
tCAC
t LZ
t HZ
t HZ
VALID
DATA OUT
tHZ
tHZ
VALID
DATA OUT
1664H-09
Waveforms of Fast Page Mode Write Cycle
V IH
RAS
V IL
V IH
UCAS, LCAS
V IL
V IH
ADDRESS
V IL
V IH
WE
V IL
t AR t RP
t RASP
t CRP
t RCD
t PC
t CAS
t CP
t CAS
t RSH (W)
t CAS
t RAH
tASR
t CSH
t ASC
t CAH
ROW
ADD
t RAD
t WCS
COLUMN
ADDRESS
t CWL
t WCS
t WCH
t WP
tASC
t CAH
COLUMN
ADDRESS
t CWL
t WCS
t WCH
t WP
t CAR
t CAH
COLUMN
ADDRESS
t CWL
t RWL
t WCH
t WP
t CRP
VIH
OE
VIL
V IH
I/O
V IL
t DS t DS
t DS tDH
tDH tDH
VALID
DATA IN
OPEN
VALID
DATA IN
VALID
DATA IN
OPEN
1664H-10
Don’t Care
Undefined
V53C1664H Rev. 1.0 February 1998
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