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PDF TC1130 Data sheet ( Hoja de datos )
| Número de pieza | TC1130 | |
| Descripción | 32-Bit Single-Chip Microcontroller | |
| Fabricantes | Infineon | |
| Logotipo |  |
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Data Sheet, V0.3, Sep. 2003
TC1130
32-Bit Single-Chip Microcontroller
Microcontrollers
Never stop thinking.
1 page  
32-Bit Single-Chip Microcontroller
TriCore Family
TC1130
Advance Information
• High Performance 32-bit TriCore V1.3 CPU with 4-Stage Pipeline
• Floating Point Unit (FPU)
• Dual Issue super-scalar implementation
– MAC Instruction maximum triple issue
• Circular Buffer and bit-reverse addressing modes for DSP algorithms
• Flexible multi-master interrupt system
• Very fast interrupt response time
• Hardware controlled context switch for task switch and interrupts
• Memory Management Unit (MMU)
• On-chip Memory
– 32 KByte Data Memory (SPRAM)
– 32 KByte Code Memory (SPRAM)
– 16 KByte Instruction Cache (ICACHE).
– 64KByte SRAM Data Memory Unit (DMU)
– 16 KByte Boot ROM
• On-chip Bus Systems
– 64-Bit High Performance Local Memory Bus (LMB) for fast access between caches
and on-local memories and FPI Interface
– On-chip Flexible Peripheral Interconnect Buses (FPI) for interconnections of
functional units
• DMA Controller with 8 channels for data transfer operations between peripheral units
and memory locations
– Two high speed Micro Link Interfaces (MLI0/1) for controller communication and
emulation
• Flexible External Bus Interface Unit (EBU) to access external data memories
• One Multifunctional General Purpose Timer Units (GPTU) with three 32-bit timer/
counters
• Two Capture and Compare units (CCU60/1) for PWM signal generation, each with
– 3-channel, 16 bit Capture and Compare unit
– 1-channel, 16 bit Compare unit
• Three Asynchronous/Synchronous Serial Channels (ASC0/1/2) with baudrate
generator, parity, framing and overrun error detection, support FIFO and IrDA data
transmission
• Two High Speed Synchronous Serial Channels (SSC0/1) with programmable data
length, FIFO support and shift direction
• One MultiCAN Module with four CAN nodes and 64 message buffers for high
efficiency data handling
• Fast Ethernet Controller with 10/100 Mbps MII-Based physical devices support
Data Sheet
1 V0.3, 2003-09
5 Page 
TC1130
Table 1
Symbol
P0.12
P0.13
P0.14
P0.15
Pin Definitions and Functions(cont’d)
Pin In PU/ Functions
Out PD1)
P9 I PUC RXDCAN2 CAN node 2 receiver input
I
RCLK0A
MLI0 receive channel clock input A
I
REQ4
External Trigger Input 4
P8 O PUC TXDCAN2 CAN node 2 transmitter output
I
REQ5
External Trigger Input 5
O RREADY0A MLI0 receive channel ready output A
N8 I PUC RXDCAN3 CAN node 3 receiver input
I
REQ6
External Trigger Input 6
I RVALID0A MLI0 receive channel valid input A
P7 O PUC TXDCAN3 CAN node 3 transmitter output
I
REQ7
External Trigger Input 7
I RDATA0A MLI0 receive channel data input A
Data Sheet
7 V0.3, 2003-09
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet TC1130.PDF ] | |
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