PDF ATC18RHA Data sheet ( Hoja de datos )

Número de pieza	ATC18RHA
Descripción	Rad. Hard 0.18 Um CMOS Cell-based ASIC for Space Use
Fabricantes	ATMEL Corporation
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No Preview Available ! Features • Comprehensive Library of Standard Logic and I/O Cells • ATC18RHA Core and I/O Cells Designed to Operate with VDD = 1.8V Sparing 0.15V as Main Target Operating Conditions • IO33 Pad Libraries Provide Interfaces to 3V Environments • Memory Cells Compiled to the Precise Requirements of the Design • EDAC Library • SEU Hardened DFF’s • Cold Sparring Buffers • High Speed LVDS Buffers • PCI Buffers • Predefined Die Sizes to Accommodate Specified Packages and ESA (European Space Agency) Multi-project Wafer Services • MQFP Package Up to 352 Pins (340 Signal Pins) • MCGA Packages Up to 625 Pins (581 Signal Pins) • Assurance Programs Will Allow – Testing Flight Models to SCC B and QML Q & V – Monitoring Heavy Ions Latch-up Immunity and Total Dose Capability Better than 100 Krads. Description The Atmel ATC18RHA is fabricated on a proprietary 0.18 µm, up to six-layer-metal CMOS process intended for use with a supply voltage of 1.8V ± 0.15V. Table 1 shows the range for that Atmel library cells have been characterized. Table 1. Recommended Operating Conditions Symbol Parameter Conditions Min Typ Max Unit VDD VDD3.3 VI VO TEMP DC Supply Voltage Core and Standard I/Os 1.65 1.8 1.95 DC Supply Voltage 3V Interface I/Os 3 3.3 3.6 DC Input Voltage DC Output Voltage Operating Free Air Temperature Range Military 0 VDD 0 VDD -55 +125 V V V V °C The Atmel cell libraries and megacell compilers have been designed in order to be compatible with each other. Simulation representations exist for three types of operat- ing conditions. They correspond to three characterization conditions defined as follows: • MIN conditions: – TJ = -55°C – VDD (cell) = 1.95V – Process = fast • TYP conditions: – TJ = +25°C – VDD (cell) = 1.8V – Process = typ • MAX conditions: – TJ = +125°C – VDD (cell) = 1.65V – Process = slow Rad. Hard 0.18 µm CMOS Cell-based ASIC for Space Use ATC18RHA Advance Information Rev. 4261A–AERO–07/03 1 1 page Design Flow ATC18RHA Though only MODELSIM and NCSIM will be used as the golden simulators, the design kit will inlcude the data and libraries needed for the following tools: Tool GATEAID2® MODELSIM® NCSIM® DESIGN COMPILER® BUILDGATES® POWER COMPILER DFT SUITE FE-ULTRA PRIMETIME® FORMALITY Supplier Atmel Mentor Cadence Synopsys® Cadence® Synopsys Mentor® Cadence Synopsys Synopsys Purpose Atmel Support tools VHDL®/VITAL® RTL + gate level simulation VERILOG® RTL + gate level simulation HDL synthesis HDL synthesis Synthesis power optimization Scan+ATPG (FastScan), JTAG (BSD- Architect), BIST (MBIST-Architect) Floor-planning, physical knowledgeable synthesis, layout prototyping Static timing analysis Equivalence checking, formal proof The Design flow can be described in two sections: • The front-end done at the customer’s premises • The back-end at Atmel Technical Centers, provided that the front-end activity has been validated and accepted by Atmel during the Logic Review (LR) meeting. The following table lists the activities and tools that will be used during the front-end design. Function Rtl Simulation Code Coverage Rtl to Gate Synthesis Power Optimization Power Analysis Test Insertion + Atpg Gate Level Simulation Netlist Translation Design Rules Check Tool MODELSIM NC-SIM VHDL-COVER DESIGN-COMPILER BUILD-GATES POWER-COMPILER PRIME-POWER DFT-SUITE MODELSIM NC-SIM NETCVT STAR Supplier Mentor Cadence Transeda Synopsys Cadence Synopsys Synopsys Mentor Mentor Cadence Atmel Atmel 4261A–AERO–07/03 5 5 Page

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ATC18RHA	Rad. Hard 0.18 Um CMOS Cell-based ASIC for Space Use	ATMEL Corporation

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