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Motorola Semiconductors - TMOS POWER FET 15 AMPERES

Numéro de référence MTB15N06V
Description TMOS POWER FET 15 AMPERES
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MTB15N06V fiche technique
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
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Designer's Data Sheet
TMOS V
Power Field Effect Transistor
D2PAK for Surface Mount
N–Channel Enhancement–Mode Silicon Gate
TMOS V is a new technology designed to achieve an on–resistance
area product about one–half that of standard MOSFETs. This new
technology more than doubles the present cell density of our 50
and 60 volt TMOS devices. Just as with our TMOS E–FET designs,
TMOS V is designed to withstand high energy in the avalanche and
commutation modes. Designed for low voltage, high speed
switching applications in power supplies, converters and power
motor controls, these devices are particularly well suited for bridge
circuits where diode speed and commutating safe operating areas
are critical and offer additional safety margin against unexpected
voltage transients.
New Features of TMOS V
On–resistance Area Product about One–half that of Standard
MOSFETs with New Low Voltage, Low RDS(on) Technology
Faster Switching than E–FET Predecessors
G
Features Common to TMOS V and TMOS E–FETs
Avalanche Energy Specified
IDSS and VDS(on) Specified at Elevated Temperature
Static Parameters are the Same for both TMOS V and TMOS E–FET
Surface Mount Package Available in 16 mm 13–inch/2500 Unit Tape & Reel,
Add T4 Suffix to Part Number
D
TM
S
MTB15N06V
TMOS POWER FET
15 AMPERES
60 VOLTS
RDS(on) = 0.12 OHM
CASE 418B–02, Style 2
D2PAK
MAXIMUM RATINGS (TC = 25°C unless otherwise noted)
Rating
Symbol
Value
Unit
Drain–Source Voltage
VDSS 60 Vdc
Drain–Gate Voltage (RGS = 1.0 M)
VDGR 60 Vdc
Gate–Source Voltage — Continuous
Gate–Source Voltage — Non–Repetitive (tp 10 ms)
VGS
± 20 Vdc
VGSM ± 25 Vpk
Drain Current — Continuous @ 25°C
Drain Current — Continuous @ 100°C
Drain Current — Single Pulse (tp 10 µs)
ID 15 Adc
ID 8.7
IDM 45 Apk
Total Power Dissipation @ 25°C
Derate above 25°C
Total Power Dissipation @ TA = 25°C (1)
PD 55 Watts
0.37 W/°C
3.0 Watts
Operating and Storage Temperature Range
TJ, Tstg – 55 to 175 °C
Single Pulse Drain–to–Source Avalanche Energy — Starting TJ = 25°C
(VDD = 25 Vdc, VGS = 10 Vdc, IL = 15 Apk, L = 1.0 mH, RG = 25 )
EAS 113 mJ
Thermal Resistance — Junction to Case
Thermal Resistance — Junction to Ambient
Thermal Resistance — Junction to Ambient (1)
RθJC
RθJA
RθJA
2.73 °C/W
62.5
50
Maximum Lead Temperature for Soldering Purposes, 1/8from case for 10 seconds
(1) When surface mounted to an FR4 board using the minimum recommended pad size.
TL 260 °C
Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.
Designer’s is a trademark of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
Thermal Clad is a trademark of the Bergquist Company.
REV 2
© MMoototororloa,laIncT.M19O96S Power MOSFET Transistor Device Data
1

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