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PDF MTV230M64 Data sheet ( Hoja de datos )
| Número de pieza | MTV230M64 | |
| Descripción | 8051 Embedded Micro Controller | |
| Fabricantes | Myson Century | |
| Logotipo |  |
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MTV230M64
8051 Embedded Micro Controller with Flash OSD and ISP
FEATURES
• 8051 core, 12MHz operating frequency with double CPU clock option, 3.3V power supply.
• 1024-byte RAM, 64K-byte program Flash-ROM.
• Maximum 4 channels of 5V open-drain PWM DAC.
• Maximum 32 bi-directional I/O pins.
• SYNC processor for composite separation/insertion, H/V polarity/frequency check and polarity adjustment.
• Built-in low power reset circuit.
• Compliant with VESA DDC2B/2Bi/2B+ standard.
• Dual slave IIC addresses.
• Single master IIC interface for internal device communication.
• Maximum 4-channel 6-bit ADC.
• Watchdog timer with programmable interval.
• OSD controller features:
. Full-screen display consists of 15 (rows) by 30 (columns) characters.
. Programmable OSD menu positioning for display screen center.
. 512 Flash-ROM fonts, with 12x18 dot matrix, including 480 standard fonts and 32 multi-color fonts.
. 15 character foreground color and 7 character background color selectable character by character.
. Character (per row) and window intensity control.
. Character bordering, shadowing and blinking effect.
. Character height control (18 to 71 lines), double height and/or width control.
. 4 programmable windows with multi-level operation and programmable shadowing width/height/color.
• In System Programming function (ISP).
• 42-pin SDIP or 44-pin PLCC/QFP package.
GENERAL DESCRIPTIONS
The MTV230M64 micro-controller is an 8051 CPU core embedded device specially tailored to LCD Monitor
applications. It includes an 8051 CPU core, 1024-byte SRAM, OSD controller, 4 built-in PWM DACs, VESA
DDC interface, 4-channel A/D converter, a 64K-byte internal program Flash-ROM and a 9K-word internal OSD
character Flash-ROM.
BLOCK DIAGRAM
P1.0-7
P3.0-2
P3.4-5
P4.0-7
P5.0-7
P0.0-7
P2.0-3
8051
CORE
RD
WR
ALE
INT1
RST
X1
X2
P0.0-7
P2.0-3
RD
WR
ALE
INT1
XFR
AD0-3 ADC
PWM DAC
DA0-3
OSD
CONTROL
OSDHS
OSDVS
XIN
ROUT
GOUT
BOUT
FBKG
INT
H/VSYNC
CONTROL
HSYNC
VSYNC
HBLANK
VBLANK
DDC & IIC
INTERFACE
ISCL
ISDA
HSCL
HSDA
Myson Century, Inc.
Taiwan:
USA:
No. 2, Industry East Rd. III,
1485 Saratoga Ave. #200
Science-Based Industrial Park, Hsin-Chu, Taiwan San Jose, CA, 95129
Tel: 886-3-5784866 Fax: 886-3-5784349
Tel: 408-973-8388 Fax: 408-973-9388
www.myson.com.tw
Rev. 1.3 September 2002
Mask Ver. AE
Page 1 of 31
1 page  
MTV230M64
FUNCTIONAL DESCRIPTIONS
1. 8051 CPU Core
The CPU core of MTV230M64 is compatible with the industry standard 8051, which includes 256 bytes RAM,
Special Function Registers (SFR), two timers, five interrupt sources and serial interface. The CPU core fetches
its program code from the 64K bytes Flash in MTV230M64. It use Port0 and Port2 to access the “external
special function register” (XFR) and external auxiliary RAM (AUXRAM).
The CPU core can run at double rate when FclkE is set. Once the bit is set, the CPU runs as if a 24MHz X’tal is
applied on MTV230M64, but the peripherals (IIC, DDC, H/V processor …) still run at the original frequency.
Note: All registers listed in this document reside in 8051’s external RAM area (XFR). For internal RAM memory
map please refer to 8051 spec.
2. Memory Allocation
2.1 Internal Special Function Registers (SFR)
The SFR is a group of registers that are the same as standard 8051.
2.2 Internal RAM
There are total 256 bytes internal RAM in MTV230M64, the same as standard 8052.
2.3 External Special Function Registers (XFR)
The XFR is a group of registers allocated in the 8051 external RAM area F00h - FFFh. These registers are used
for OSD control or other special function. Program can use "MOVX" instruction to access these registers.
2.4 Auxiliary RAM (AUXRAM)
There are total 768 bytes auxiliary RAM allocated in the 8051 external RAM area 800h - AFFh. Program can
use "MOVX" instruction to access the AUXRAM.
FFh Internal RAM
SFR
Accessible by
indirect
addressing only
(Using
MOV A,@Ri
instruction)
80h
7Fh Internal RAM
Accessible by
direct addressing
Accessible by
direct and indirect
addressing
00h
FFFh
XFR
Accessible by
indirect external
RAM addressing
(Using MOVX
instruction)
F00h
AFFh
AUXRAM
Accessible by
indirect external
RAM addressing
(Using MOVX
instruction
800h
Page 5 of 31
5 Page 
MTV230M64
VCNTL
HVCTR0
HVCTR3
HVCTR4
INTFLG
INTEN
F44h (r) VF7
F40h (w) C1
F43h (w)
F44h (w)
F48h (r/w) HPRchg
F49h (w) EHPR
VF6
C0
CLPEG
VPRchg
EVPR
VF5
NoHins
CLPPO
HPLchg
EHPL
VF4
CLPW2
VPLchg
EVPL
VF3
CLPW1
HFchg
EHF
VF2
CLPW0
VFchg
EVF
VF1
HBpl
DF
VF0
VBpl
Vsync
EVsync
HVSTUS (r) : The status of polarity, present and static level for HSYNC and VSYNC.
CVpre = 1 → The extracted CVSYNC is present.
= 0 → The extracted CVSYNC is not present.
Hpol = 1 → HSYNC input is positive polarity.
= 0 → HSYNC input is negative polarity.
Vpol = 1 → VSYNC (CVSYNC) is positive polarity.
= 0 → VSYNC (CVSYNC) is negative polarity.
Hpre = 1 → HSYNC input is present.
= 0 → HSYNC input is not present.
Vpre = 1 → VSYNC input is present.
= 0 → VSYNC input is not present.
Hoff* = 1 → HSYNC input's off level is high.
= 0 → HSYNC input's off level is low.
Voff* = 1 → VSYNC input's off level is high.
= 0 → VSYNC input's off level is low.
*Hoff and Voff are valid when Hpre=0 or Vpre=0.
HCNTH (r) : H-Freq counter's high bits.
Hovf = 1 → H-Freq counter is overflow, this bit is clear by H/W when condition removed.
HF13 - HF8 : 6 high bits of H-Freq counter.
HCNTL (r) : H-Freq counter's low byte.
VCNTH (r) : V-Freq counter's high bits.
Vovf = 1
VF11 - 8 :
→ V-Freq counter is overflow, this bit is clear by H/W when condition removed.
4 high bits of V-Freq counter.
VCNTL (r) : V-Freq counter's low byte.
HVCTR0 (w) : H/V SYNC processor control register 0.
C1, C0 = 1,1 → Select CVSYNC as the polarity, freq and VBLANK source.
= 1,0 → Select VSYNC as the polarity, freq and VBLANK source.
= 0,0 → Disable composite function.
= 0,1 → H/W auto switch to CVSYNC when CVpre=1 and VSpre=0.
NoHins = 1 → HBLANK has no insert pulse in composite mode.
= 0 → HBLANK has insert pulse in composite mode.
HBpl = 1 → negative polarity HBLANK output.
= 0 → positive polarity HBLANK output.
VBpl = 1 → negative polarity VBLANK output.
= 0 → positive polarity VBLANK output.
HVCTR3 (w) : HSYNC clamp pulse control register.
CLPEG = 1 → Clamp pulse follows HSYNC leading edge.
= 0 → Clamp pulse follows HSYNC trailing edge.
CLPPO = 1 → Positive polarity clamp pulse output.
= 0 → Negative polarity clamp pulse output.
Page 11 of 31
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet MTV230M64.PDF ] | |
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